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  • STREX always clears the exclusive access tag

    Hello everybody,

    Section 18.8 Exclusive access of Cortex-A Series Programmer's Guide says the following:

    STREX can be considered as a conditional store. The store is performed only if the physical address is still marked as exclusive access (this means…

  • MRS/MSR (Banked register)

    What can be accessed by MRS/MSR in user mode?

    In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

    B9.3.10      MSR (Banked register)
    cond  0 0 0 1 0 R 0 0        M1      …

  • Still more stupid questions on Cortex-A7 instruction set

    I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found

    an answer to in ARMv7-A/R ARM Issue C.

    How is this special?

    LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD<c>_<Rt>,_<Rt2>,_[PC,_#-0]_Special_case…

  • Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

    Hello,

    I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…