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  • Arm Cortex-A8 program flow prediction

    I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code:

    char SecretDispatcher[256 * 512];
int counter = 0;

//evicting SecretDispatcher from cache
...

while(counter < (512 * 9 + 1))
{
    //evict…

  • The merit of data cache cleaning

    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

  • Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

    Hi Experts,

    I'm reading white paper for ARMv7 and ARMv8.

    but when i reading cache part and memory re-ordering, i have silly questions.....

    Suppose there are below instructions..

     

    Core A:

         STR R0, [Msg]

         STR R1, [Something…

  • Feature wise comparision for Cortex A series processors

    Hi Experts,

    Is there any document on feature wise comparison chart on the Cortex A series of processors ?

    Like,

    Cache for Cortex A8/9/52...

    MMU for cortex A8/9/52..

  • ARM Cortex A9 flush cache

    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

    Is it doable from user mode?

    Processor: ARM Cortex A9

    OS: Linaro Linux

  • ARMv7 CortexA9 Cache Policy - No allocate ?

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

  • Data synchronization Barrier and cache.

    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before starting copy by DMA, I clean data cache by MVA…

  • Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

    Hello,

    Consider following scenario:

    1. A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache.
    2. Now, the s/w writes to the first word in the page. Let's assume valid…