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  • Development of Arm based systems with Synopsys Virtual Prototyping: Anytime, Anywhere!

    ** Sharing this article from Kamal Desai, Product Marketing Manager at Synopsys

    Around the world thousands of engineers have been asked to work from home. Temporarily gone are the days of global travel, and with it the ‘traditional’ development and global…

  • Autodetect SDRAM size in uBoot Bootloader via ARMv7 processor exception handler

    Hi There,

    I am writing some bootload code for the TI Sitara AM5726 processor which has Dual Arm-v7 Cortex-A15  cores. The uBoot bootloader is the code that runs before starting the Linux Kernel and is responsible for configuring the extents of the SDRAM…

  • How to start cpu in ARMv7 baremetal environment?

    I am using an Allwinner H3 SoC (on a zeropi board) and I want to start up a secondary core without using an OS.
    I am trying to use the SMC call CPU_ON, using the following code:


    smc_call(0x84000003, 0x02, (void*)blink, 0);


    Where I use the assembler routine…

  • Why does Arm still support short descriptors?

    What I'm asking is ARM Architecture Reference Manual for ARMv8-A  says in AArch32 there are two translation table formats:

    • Short descriptors: 32 bit
    • Long descriptors: 64 bit

    On page G4-4726 (Issue B.b), there are various points listed that each…

  • How to connect to an embedded linux target for remote debugging?

    I'm trying to debug the "xaos linux example" included with ARM Development Studio on my ODROID-XU4 embedded linux platform. For this purpose, I'm following this tutorial https://developer.arm.com/tools-and-software/embedded/legacy-tools…

  • Cross-compiling and building a simple Hello world application for running on Heterogenous architecture

    I am new to ARM

    I would like to cross-compile a simple Hello world c++ code for Linux distribution in order to debug and run it on my Hardkernel ODROID-XU4 board. For this purpose I'm following this tutorial https://developer.arm.com/tools-and-software…

  • Cannot install DS-5 Community edition on ODROID-XU4

    I downloaded the DS-5 community edition for the ARM website to run it on my ODROID-XU4 (ubuntu 18.04) which is an Armv7-A 32-bits platform. When I run the install shell, I get the following error 

    odroid@odroid:~/Downloads/ds5-ce-linux64-29rel1$ ./install…

  • Secure SPI : STM32MP157-DK1 board

    Hey everyone,

    I am working on STM32MP157-DK1 with trustzone cortex-A.
    I want to use the SPI in secure side, but it's possible only with SPI 6 that is not mapped to the outside.


    It's possible to activate SPI (1 ... 5) peripherals in secure side ? if…

  • Running two bare-metal programs on two separate cores in Cortex-A9

    Hello,

    I have run two different bare-metal programs on two corresponding ARM cores in Cyclone V (Cortex-A9) in DS5 using JTAG line. The SDRAM is shared between the two cores as is evident from the cache settings which is set to "shared" by default. Core…

  • Arm Cortex-A8 program flow prediction

    I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code:

    char SecretDispatcher[256 * 512];
int counter = 0;

//evicting SecretDispatcher from cache
...

while(counter < (512 * 9 + 1))
{
    //evict…

  • What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm?

    Hi All,

    What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm? I know that they say it is compatible with ARMv7/8 ISA.

    Regards

    Nitin

  • How get ARMv7 cache size

    Hi everybody!!

    I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

    In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…

  • ARMv7-A: What is "Fault not on a stage 2 translation for a stage 1 translation table walk"?

    Hi all,

    I'm trying to boot Linux on my hypervisor like environment.

    In booting process, unexpected hyper trap was occurred and became hyp mode.

    In hyp mode, the Hyp Syndrome Register (HSR) value is 0x93830006.

    According to the manual, this meant "Fault…

  • Spin-lock implementation for Aarch64 -- how to enforce acquire semantics?

    Here is a minimal C implementation of a spinlock "lock" operation using GCC's built-in atomics:

    #include <stdbool.h>

void spin_lock(bool *l) {
  while (__atomic_test_and_set(l, __ATOMIC_ACQUIRE))
    ;
}

    I am concerned…

  • float behaivior on AARCH64

    Hello,

    forgive me if my question is a litte bit weak in content and linguistic. I'm only a Hobbyist and english is not my nativ.

    I'm trying to compile an App from Einstein@Home for AARCH64 using GCC. Einstein@Home is a DC-Projekt using Boinc. The App…

  • arm v7AR debug architecture DCC register access

    Dear sirs,

    The ARM v7ar manual says that DCC data registers DBGDTRTX and DBGDTRRX have RW attributes from external view.

    It confuses me why DBGDTRTX can be written from external debugger. what is the purpose for this function?

    The same confusion to DBGDTRRX…

  • Where is hardware interrupt latency documented for the ARMv8 Cortex-A53?

    Need specific references to the hardware interrupt latency for the ARMv8 Cortex-A53.  interrupt latency from when an interrupt is triggered to when the ISR is initially invoked, but not including operating system, kernel, or application latency.

    …

  • cortex-A15 instruction set and optimization ways on this platform?

    Dear,

    I am an greenhand developer on cortex-a15.

    now I need some specification as follows:

    where I can get the instruction set of cortex-A15?

    are there some documents about optimization technology on cortex-A15(image processing optimization)

    Thanks a lot.

    …

  • Is the single or multicore Cortex-A5 suitable for the Mali500 and Mali550?

    There is no cortex-A5 in the related products tab.

    Mali-V550 - ARM

  • Why does FPU performance differ in AArch64 and AArch32 with Cortex-A53?

    Hello experts,


    I have come to having a question.
    VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
    The software can be downloaded from the following link…

  • Is there a list of all opcodes mnemonics understood by each architecture?

    Greetings,

    I'm currently experimenting with Jekyll and I'm trying to make an GNU ARM Assembly syntax highlighter for Rouge.

    However, the ARM Architecture Reference Manual does not seem to have a simple complete list of mnemonics. They are all…

  • MMU deactivation and I-Cache / Branch Predictor

    Hi !

    In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible to map it and the devices correctly due to restriction…

  • Cortex A code / function alignment

    Hi !

    I am writing assembly code for some ARMv7a and ARMv8a CPU. I know that code has to be 4 bytes aligned, but I saw in several places (uboot/linux) the ".align 4" GCC directive, which will align to 2**4 = 16 bytes.

    When writing code that will…

  • 8-byte stack alignment for ARM Cortex-A9

    Hello everbody,


    as i have written before in "Compability between architecture ARMv5TE and ARMv7-A", we want to change our Platform-Processor from ARM946E-S to an ARM Cortex-A9. The next Point in our risk disclosure ist the stack alignment.

    Our…

  • Why I can't find the performance monitoring event for all Instructions count? How to get instructions event for my ARMV7 Cortex-A9 by PMU?

    Can anyone help?