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  • Concurrent Interrupts

    Hi All,

    Im new to the Arm Community and Arm processors (newbie), and my question is as follows: Atmel ATSAMD20e  implements ARM cortex M0+ processor based on ARMv6 architecture. It allows upto 32 external interrupts, with the interrupt signals connected…

  • Can I use EXEC_RETURN on M0 outside of an exeception for contect switches?

    I have initialized stacks for various tasks with content as expected on SVC interrupts.  I'm not able to dispatch an initial task via the "normal" dispatch function.  On this first dispatch, the processor is not in an exception handler, but the LR is…

  • cmsis NVIC question.

    Hello, Everybody. I have several questions.

    1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

    2. I would like…

  • Debugging a Cortex-M0 Hard Fault

  • Cortex-M0+ privileged/unprivileged extensions

    Hi all,

    According with ARMv6-M architecture reference manual, it supports two operation modes, handler mode and thread mode.

    - "execution in handler mode is always privileged."

    - "execution in thread mode can be privileged or unprivileged, depending…

  • Understanding of the clock cycle activity for LPC1114

    Hello, 

    I am now working with the LPC1114 which utilizes the ARM CORTEX M0 architecture. I have one question about the instruction set summary of the ARMv6M Thumb instruction set. I want to know what the processor does during each single clock cycle for…

  • cortex m0

    The ARMv6-M Architecture Reference Manual for my country is not aviable the dowload from the ARM oficial page, i beginin to stady the cortex M0 if any cand help me whit eny information abuat the micro please contact me   thanks

  • cortex m0

    I need the ARMv6-M Architecture Reference Manual and ebrising abaut the cortex m0

  • Cortex-m0 instructions and core registers immediete values

    Hi, i have just got a cortex-m0(LPC1114) based dev board. I'm reading about the architecture and instructions. My understanding is that it supports most thumb 16-bit instructions and a handful thumb-2 32-bit instructions. If the processor has a 32-bit…