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  • Concurrent Interrupts

    Hi All,

    Im new to the Arm Community and Arm processors (newbie), and my question is as follows: Atmel ATSAMD20e  implements ARM cortex M0+ processor based on ARMv6 architecture. It allows upto 32 external interrupts, with the interrupt signals connected…

  • Can I use EXEC_RETURN on M0 outside of an exeception for contect switches?

    I have initialized stacks for various tasks with content as expected on SVC interrupts.  I'm not able to dispatch an initial task via the "normal" dispatch function.  On this first dispatch, the processor is not in an exception handler, but the LR is…

  • What is the meaning of a 64 bit aligned stack pointer address?

    According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in  it says:

    "Although the processor hardware allows SP to be at any word aligned address at function boundaries, standard programming practice…

  • cortex m0

    The ARMv6-M Architecture Reference Manual for my country is not aviable the dowload from the ARM oficial page, i beginin to stady the cortex M0 if any cand help me whit eny information abuat the micro please contact me   thanks

  • cmsis NVIC question.

    Hello, Everybody. I have several questions.

    1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

    2. I would like…

  • Cortex-M0 Thumb-2 instruction: Is this instruction valid?

    STM     r0!, {}

    I have looked at Thumb2 instruction set web but I can't find the behaviour of STM command if the reglist is empty.

    Thanks in advance.

  • CPU Reset during a Debug session

    Hi All,

    I am trying to reset the CPU in the middle of a debugging session. I am using Application Interrupt and Reset control register by setting the SysResetReq bit in the SCB block. (this preserves the current debugging session also).

    However, as I am…

  • Debugging a Cortex-M0 Hard Fault

  • cortex m0

    I need the ARMv6-M Architecture Reference Manual and ebrising abaut the cortex m0

  • Why thumb code can only access r0-r7?

    Hi Sir,

    I want to know why thumb code can only access r0-r7, which described in ATPCS?

    Thanks and best regards,

    Wenchuan

  • Cortex-M0+ privileged/unprivileged extensions

    Hi all,

    According with ARMv6-M architecture reference manual, it supports two operation modes, handler mode and thread mode.

    - "execution in handler mode is always privileged."

    - "execution in thread mode can be privileged or unprivileged, depending…

  • Understanding of the clock cycle activity for LPC1114

    Hello, 

    I am now working with the LPC1114 which utilizes the ARM CORTEX M0 architecture. I have one question about the instruction set summary of the ARMv6M Thumb instruction set. I want to know what the processor does during each single clock cycle for…

  • ARMv6-M vs ARMv7-M - Unpacking the Microcontrollers

    This article is a follow-on to Navigating the Cortex Maze. As a high-level overview, the earlier article provides an easy way-in to the ARM processor range. It covers Cortex-A (architecture ARMv7-A), Cortex-R (ARMv7-R) and Cortex-M (ARMv7-M).

    But the…

  • Cortex-m0 instructions and core registers immediete values

    Hi, i have just got a cortex-m0(LPC1114) based dev board. I'm reading about the architecture and instructions. My understanding is that it supports most thumb 16-bit instructions and a handful thumb-2 32-bit instructions. If the processor has a 32-bit…