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  • Relaxed Persist Ordering Using Strand Persistency

    As the lockdown measures get relaxed gradually in many parts of the world, it is clear that stricter lockdown rules can help governments manage the pandemic but can also hurt the economy. Likewise, stricter ordering rules for memory operations help simplify programming…

  • Enabling top-byte ignore on ARMv8 Base FVP

    Greetings,

    I would like to enable top-byte ignore support on the FVP. I would be grateful on any guidelines on how to do that. Thank you very much!

    Best regards,

    Mohannad Ismail

  • ARM Base FVP freezes if left idle

    Greetings,

    If I leave the FVP idle for around 1 hour and come back to it, I find that it freezes and have to stop the simulation and re-run it again. What is the possible reason for this and is there a way to stop that from happening? Thank you for your…

  • Debugging on ARM Base FVP

    Hello,

    I would like to know how do I attach gdbserver to my ARM Base FVP for debugging. All tutorials online explain using DS-5. I would like to use gdb since I am more comfortable with it. I already enabled networking on my FVP.

    Thanks for your help…

  • Some questions regarding ARMv8 hardware features

    Hello, 

    I am a PhD student doing research using the ARMv8 hardware features. I have a few questions regarding them. Some of these may seem a bit trivial, but I like to be a bit more thorough and confirm my understanding, and ARM is relatively new to me…

  • Developments in the Arm A-Profile Architecture: Armv8.6-A

    The Arm Architecture is continually evolving to meet the needs of our ecosystem partners. This blog gives a high-level overview of some of the changes being introduced in Armv8.6-A.

    The enhancements to the architecture provide more efficient processing…

  • BFloat16 processing for Neural Networks on Armv8-A

    Neural Networks are a key component of Machine Learning (ML) applications. Project Trillium, Arm’s heterogeneous ML platform, provides a range of technologies in this field, including instructions that accelerate such applications running on CPUs based…

  • How does the NEON access Memory?

    Note: This was originally posted on 5th May 2008 at http://forums.arm.com

    I have a question about how to get the maximum calculation capability of NEON. In our video processing application, we should access several frame video. Then if the video is HD…

  • LDR Instruction

    Note: This was originally posted on 5th November 2008 at http://forums.arm.com

    Hi all,
            I am new to the thumb-2 instruction set. In one of my sample code
    I noticed a instruction
             LDR r0, =0x12345678;…

  • A List of books about ARM Architecture

    Below, I suggest a list of books and papers about the Arm architecture.

    In this shortlist, I listed the books I'm reading or want to read. How I missed an orientation as well as order suggestions to read them, I thought it would be worth publish it here…

  • What purpose does BURST feature in AHB serve?

    I am not able to see any visible improvements due to the BURST transfers. The same BURST transfer could be done through multiple SINGLE transfers, in the same number of cycles. Then what is te advantage of having BURST transfers?

  • Introducing high performance device virtualization: Approach to standardization

    Author: Francisco Socal, Senior Product Manager, Architecture and Technology Group, Arm

    In this blog we introduce our approach to accelerators and device virtualization with a view to agreeing standards.

    The complexity and performance requirements of…

  • AArch64 code execution on Raspberry Pi3.

    Hello everybody,

    does everyone know whether Raspberry Pi3 can execute 64bit applications?

    Even reading some articles, I am uncertain the following things.

    Please let me know the answers.

    1. Is Raspbian for Raspberry Pi3 compiled by AArch64 architecture?

    2…

  • Xen/dom0 on Juno

    Hey all,

    I have been playing around with Xen and Dom0 on a Juno r0 board. Currently dom0 is failing to initailize USB. This is an issue because the rootfs depends on the usb.

    usb 1-1: new high-speed USB device number 2 using ehci-platform

    usb 1-1: device…

  • How Does the Secure World Work with Multicore System?

    Hi experts,

     

    From my experience, for the single-core architecture, once we enter the secure world, the normal world would be paused. However, I'm not sure how does secure world is scheduled for the multicore system? 

    Do we still have to pause the normal…

  • Issue of Building the OpenEmbedded Filesysytem from Source for Juno

    Hi , ,

     

    I'm currently using a Juno r1 board and I'm running the Linaro's deliverables on my board. 

    Recently I want to build the OpenEmbedded system by myself so I checked the instruction. However, after I finished the…

  • Why GNU ARM Toolchain objcopy didn't redefine and strip symbols, what a possible workaround?

    I have Android shared library with armeabi-v7 architecture, and I need to rename some functions inside this.

    Firstly, I tried ARM toolchain v4.9 of Android NDK.

    I tried:

    objcopy --redefine-sym _Z3foo1v=_Z3foo2v libTest.so libTestResult.so

    It throws no…

  • How to Get the PA instead of IPA from NS OS Kernel Module of an AArch64 device?

    Hi experts,

    Recently I want to conduct one secure-related scanning in TrustZone for some NS kernel memory.

    To do this, I need at first reporting the PA of the memory from NS kernel. My idea is developing a kernel module to achieve the goal.

    I write the 

    …

  • Is OPTEE_OS for Juno using 32-bit arch or 64-bit arch?

    Hi experts,

     

    I'm wondering do you compile the OPTEE_OS in this instruction as arm32 or AArch64? In which script do you set the compiler for the secure OS? ( I checked the file build-optee-os.sh while I find the file exports both compilers so I'm not…

  • Juno r1 Shareability Memory Attributes

    Hi experts,

     

    I'm using a Juno r1 board for some cache-related research experiment so I'm studying the related memory attributes such as cacheability and shareability.

     

    I found the manual mentioned that: " the division between inner and outer is…

  • Virtual Machine Control Structures (VMCSs) on Intel VT

    Hello everyone, 

    May I can ask you something if anyone knows, 

    Is there on ARM processors a similar function like VMCSs to save and load CPU states and registers in memory?

    I am reading about VMCSs and I am trying to find out what is the similarity of this…

  • Enter Hypervisor Mode on ARMv7 through Kernel Module

    I am trying to write a kernel module in C to bring the system in the hypervisor mode. The module is for a router, which is running OpenWrt. The architecture is ARMv7.

    When I load my module with insmod I get this error when the module comes to the hvc…

  • How to download past ARM's document.

    I want to find and download as follow document.

    > ARM Architecture Reference Manual Security Extensions Supplement

    If you have its location URL, could you please tell me it ?

    Or how can I do above ?

  • Multicore Platform General Purpose Registers

    Hi, experts ,

    I'm wondering for the multicore ARM architecture, are all CPU cores sharing one set of general purpose registers (X0 - X30) or each CPU core has its separate registers? My feeling is that each core has its own…

  • How to use the external debugging interface in Juno board?

    Hi all,

    I am trying to use one Cortex-A57 (debugger) core to debug a Cortex-A53 core (target) on Juno board. According to the armv8 architecture manual, i may halt the the target and use EDITR instruction to force the target execute instructions. So,…