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  • AXI3 data interleaving

    Hi,

    I was going through write data interleaving section in ARM AXI3 protocol. Found this statement:

    "For a slave that supports write data interleaving, the order in which it receives the first data item of each transaction must be the same as the order…

  • Use-cases of AXI3 unaligned transfers

    Hi all,

    I cannot think of a good usecase of unaligned transfers in AXI3.

    - For unaligned write, a master can anyway use aligned write + write strobes.

    - For unaligned read, a master can use aligned read, then decides which data part of the first beat…

  • RE: In read or write transaction in AXI.what happen if data transaction  is before address.

    Hii,

    In AXI 3 if  data items are written before the address comes due to register delays .....then where that data is being stored in memory because no address is being specified till now...?

    please resolve this issue...

    Thanks 

  • Difference btw AXI3 and AXI4

    Hi All ,

                Can anyone please tell the difference btw AXI3 and AXI4.

    Regards

    Muthuvenkatesh

  • Sampling on positive edge of clock of slave in AXI3

    How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation

  • AXI3 & AXI4 wrap burst length

    Hi,

    Was going through AXI spec.

    As per AXI spec:

    "AXI3 supports burst lengths of 1 to 16 transfers, for all burst types."

    "AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers. Support for all other burst types in…

  • AMBA3 AXI - Exclusive access

    1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location??

    Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID (first is 00 and second is 01) to the sam an address…

  • AMBA3 AXI Relationship Between Channels

    In the document AMBA3 AXI (3.2 Relationships between the channels)

         Two relationships that must be maintained are:

              • read data must always follow the address to which the data relates…

  • Please help about AMBA AXI 3.0

    I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0

    1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?

    2. In the FIXED…

  • hi. i wonder AMBA 3.0 AXI difference of data interleaving and write data interleaving

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.



    as you can see the first picture, slave send the read…

  • hi. i wonder AMBA 3.0 AXI handshake

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

       

    firstly, i very wonder the handshake…

  • Reason for having decouple write address, data channels in AXI4

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

  • AXI Write data interleaving

    Hello Everyone,

    [This not specific to AXI3/4] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases also?

    In case if we have 2 burst transfers with A …

  • Does AMBA 4 ACE backward compatible with AXI3?

    Does AMBA 4 ACE backward compatible with AXI3? Suppose that I don't need all the coherency features

  • AXI Protocol -  Strobe Signal Value

    how to calculate the value of strobe signal in axi?