Hello,
On exiting non-secure interrupt handler, armv8-M cm33 gets in a bad state and hangs.
I think what's happening is, on exiting non-secure handler, cpu try to restore state from a secure area, I see "sec_err_irq_mpc" fires right after non-secure irq…
I am working with a port of FreeRTOS on Arm64 soc , which is running at EL1, my goal is to perform a function call that will execute in EL0,
I have come to understand that the only way for the EL switch is to set the correct M bits of the spsr_el1…
Hi all i trying do transition from EL3 to EL2 exception ,but after ERET of EL3 mode it change the mode to EL2 , but as soon as when it will execute first instruction of EL2 , then It goes to Exception ...
This is happen for every secure to non secure transition…
I'm trying to understand how ARM architecture(ARMv8) support for faulting address in the virtualization environment. For the hypervisor, every device access from the guest must be trapped to emulate a device.
The memory access from the guest will…
I have successfully moved from EL3 to EL2. After doing some initialization I am trying to move from EL2 into EL1 with a very simple guest image. My process looks like:
Hi,
How do i configure vector table for cortex A-57?
From the documents - "The vector table has 16 entries, with each entry being 128 bytes (32 instructions) in size. The table effectively consists of 4 sets of 4 entries"
Also " Virtual…
When i power on a ARM cortex A57, How many of the 4 Exception levels will be supported?
How can i set such that only exception levels EL0 and EL1 are supported in my program? How can i activate each exception levels?
I have to set it such that normally…
Sorry for basic question,
For ARM64, we have different interrupt vector table for each mode EL3/EL2/EL1
I am wondering, how a specific IRQ is routed to given mode.
in GIC, I am not able to find such relation
Thanks
Udit
I am working on EL2 mode ARM V8 ,
Problem I am facing when I enable D-cache then I am not able to read the data.
My boot flow is EL3 to EL2 and in EL2 snippet of code is below
1 stp x29, x30 [sp,#32]
2 mrs x0, sctlr_el2
3 orr x0, x0, #CTRL_C_B…
Dear all,
As I know there are separate vectors to handle SError caused by EL0 and EL1.
My queston is follow:
Due to fact that SError is asynchronous, can I rely on fact that if cpu entered serror_el1_vector to handle SError, then SError was caused exactly…
Hi !
When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before trying to access the address ?
Best,
V.
In my last couple of blogs we built an ELF image to expose some features of the Armv8-A architecture and toolchain for embedded software development. We got to a point where we could print "hello world" to a telnet console, and enable interrupts on the…
Hi everyone,
Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.
In ARM v8 vector table, given on ARMv8-A architecture…
在ARMv8-A中，EL1/2/3除了可以自身的堆栈寄存器SP_ELn以外，还可以使用SP_EL0。
与此同时EL0也可以使用SP_EL0。
我想在EL0的应用程序应该可以通过SP_EL0，访问到EL1/2/3的数据，这岂不是不安全？
希望帮忙解答，谢谢！
Hi experts，
In ARMv8, EL1/2/3 can use either their own stack pointer, SP_ELx or SP_EL0.
SP_EL0 can be used in EL0.
why it is safe to use SP_EL0 in EL1/2/3? I think the applications in EL0 may get the data of kernel in EL1 through SP_EL0.
Can anybody…
Hi Fellows,
I want to determine in code, if the processor is in EL0 mode or not. I read CurrentEL register to do this but if my code is running from EL0, it throws an exception since we can't access CurrentEL from EL0. Is there any alternative and easy…
I want to switch stack pointer to SP0 from SP1 every time an exception is taken to EL1 on armv8. I execute MSR SPSel, #0 to do this. My question is that is it necessary to use an ISB intruction etc. after it? If yes, what are the performance…