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  • First compile, verilog files missing

    Hi,

    I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

    So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

  • NVIC and ARM asm

    Cannot configure interupts of TIM6 on stm32f103 board

    Does my NVIC configuration wrong?

    Code:

    @ stm32f103 timer & interrupt test by laper_s (from 2019-02-02)

.thumb
.cpu cortex-m3
.syntax unified

.word   0x20005000
.word   start + 1

b   start…