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  • [APB] Assert timing of PSTRB and PPROT

    Hi All,

    I have a question about assert timing of PSTRB and PPROT.

    I think APB4 spec (IHI0024C_amba_apb_protocol_spec.pdf) does not describe when PSTRB and PPROT should be asserted.
    I guess these signals should be asserted while PSEL is high like PADDR…

  • [APB] Assert timing of PSTRB and PPROT

    Hi All,

    I have a question about assert timing of PSTRB and PPROT.

    I think APB4 spec (IHI0024C_amba_apb_protocol_spec.pdf) does not describe when PSTRB and PPROT should be asserted.
    I guess these signals should be asserted while PSEL is high like PADDR…

  • questions about APB advantages

    Note: This was originally posted on 8th November 2008 at http://forums.arm.com

    Hi! dear all  :lol:
    Some APB advantages are listed in AMBA 2.0 spec. They are

    "¢ performance is improved at high-frequency operation
    "¢ performance is independent of…

  • ARM Cortex ICode, DCode, System buses

    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
    …

  • AMBA

    Hello....!!!

    Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

  • AMBA

    How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…

  • APB3 Slave responding when PSEL = 0

    Hello All,

    Here at IP Level verification we have no issues as the Master APB does not latch the PREADY, but at SOC Level with multiple APB Slaves 

    The Master performs some transaction with APB SLAVE 1 and before switching to APB SLAVE 2 , it disables the…

  • Assertion for Multiple Transfer on APB Bus

    Hi,

       Can you please help me in writing assertions to take care on multiple transfer in APB bus?

    Thanks,

    Rakesh

  • TZPC of Juno-r1

    Hi experts , ,

    I'm trying to configure some peripherals like NIC of the Juno as the secure peripherals.

    By checking the material I found that TrustZone Protection Controller(TZPC) can achieve this goal while I do not find any…

  • How can I get IP-XACT descriptions of CMSDK components?

    We use IP-XACT based automation tools, mainly for register views, so need IP-XACT description of the APB registers for the CMSDK components.

  • Can PENABLE be removed from APB as it seems redundant at IO level and same logic can be taken care of internally by Master and Slave ?

    PENABLE indicates the second and subsequent cycles of an APB transfer till PREADY goes HIGH.

    APB transfer can be considered as complete when PSEL==1 and PREADY==1 ignoring PENABLE==1 and PREADY==1 should be considered only after second and subsequent cycles…

  • AXI AHB APB quick reference cheat sheet

    Hi,

     I have tried to find a quick reference for AXI, AHB & APB to no avail, and after having to flit between the various documents and tables, I eventually created my own.

    So not sure of the legal ramifications of posting this elsewhere and whether…

  • apb 2.0 continuous transfer

    Hi All,

          Now i am focusing on the apb 2.0 specification. 

         How to perform a continuous transfer in apb 2.0 . I read some forum , But i did't get a idea.

          If anyone know the continuous transfer in apb 2.0 ,Please share the waveform . It;s easily…

  • apb protocol checker (assertions)

    How can I get apb protocol assertions on arm official site? Thanks in advance, KMK

  • why PSTRB signal in APB4 have four bits?

    PSTRB signal indicates which byte lanes to update during a write transfer.

    it shows that the bus contain valid data, when PSTRB[3:0]=1111.

    why we need bus instead of single bit PSTRB signal?

  • Why does AHB or APB support only 16 slave devices?

    I would like to know why only 16 slave device select lines are present in the AHB and APB bus architectures.

  • DesignStart Pro: APB on FPGA via Quartus Prime

    Hello,

    I try to implement the Cortex-M3 processor on an FPGA via Quartus Prime. I set up the SSE050 Subsystem and tried to connect several peripherals to the board. I want to test the functionality with a uVision project lighting some LEDs. To have access…

  • Please send the APB 3.0 spec

    Can you please send me the AMBA APB 3.0 specification for reference.

  • needs some clarification

    Hi

    i have one doubt..in apb protocols...what is the difference between wait_state and no_wait_state in apb protocopls?

  • Working frequency on AMBA- APB,AHB, AXI

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

  • Embedded World 2014 - ARM Cortex-M Processor based System Prototyping on FPGA

    Several people have asked me for the following paper I presented in Embedded World 2014:

    ARM Cortex-M Processor based System Prototyping on FPGA

    Abstract

    Many SoC designers need to design FPGA prototypes of Cortex-M series processor-based systems for…

    • 8378.zip