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  • AXI ARID AWID

    What is the size of AWID and ARIDs? On what basis size is determined? How the AxIDs are generated?

  • Synopsys supports launch of Arm AMBA 5 AXI5, ACE5 protocols with 1st source code test suite and VIP

    Through a blog post by Arm has just announced the new Arm AMBA 5 AXI5, ACE5 and ACE5-Lite protocols; you can request the the latest AMBA 5 specs through a link in that blog. These protocols are employed by Arm's latest technology, including…

  • Introducing the next generation of AXI and ACE protocols

    Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols have been implemented in Arm’s latest technology…

  • Arm Technical Training – Any time, any place

    Partner Training at Arm has been a great success over the last 15 years. It has expanded the knowledge and capabilities of our Partners’ Engineering teams by delivering classroom sessions to over 4000 attendees in 2016 alone and has helped our Partners…

  • AMBA AHB5 to AHB lite

    Hello,

     what are the additional features added or removed in AHB lite;

    regards

    Pavan

  • Can STR instruction to a device address be preemtible from IRQ

    Hi,

    I am doing a writel to a PCIe device which is taking around 3msec due to link in low power state.

    writel translates to wmb followed by STR asm instruction.

    My question is, while ARM performing STR instruction on CPUx, can any IRQ able to preempt this…

  • Cycle-accurate Performance Analysis now available for latest AMBA5

    I already shared last month some details of work we have been doing with Arm on an HPC testchip, the good news continues with our announcement of extended support for the AMBA 5 protocol family with support for CHI.b in our Cycle-accurate performance…

  • Introducing AMBA 5 CHI protocol enhancements: Specification now available

    In 2013 Arm announced the AMBA 5 CHI protocol to provide the performance and scale required for infrastructure applications such as networking and data center. The protocol has been highly successful and has been the foundation for Arm many core systems…

  • 社区用户何老师精心制作视频课程

    大家好,

    很多朋友可能知道,我们ARM社区用户藏龙卧虎,各有各的高招。他们自己还有很多宝贵的资源,可以分享给其他用户。

    今天,我推荐一下社区用户何老师的视频课程。

    何老师(何宾)是一位北京的大学教师,对于处理器,FPGA和电子科学非常了解,熟悉,他自己也为学生上课,业余时间编写ARM相关教材,在行业内很有知名度。

    最近,何老师告诉我们他分享了他的课程视频,给大家免费观看。

    希望对大家学习ARM有一定的帮助。

    以下是课程链接:

    http://edawiki.com/

    此课程适合学习Cortex-M0处理器…

  • Working frequency on AMBA- APB,AHB, AXI

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

  • AMBA

    Hello....!!!

    Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

  • AMBA AHB

    Hi ,

    In AHB specs, There is one note as below.

    Note

    Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation of the latency of accessing the bus. It is recommended…

  • AMBA AHB SLAVE MULTIPLE SPLIT RESPONSES TO SINGLE MASTER

    Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?

  • AHB slave

    1.) In AHB, When early burst termination is occurred, HRESP should be OKAY and HREADY should be high?

    2.) Is there any possibilities that if write transaction is in progress and if burst is not completed then HWRITE will be low after some clock. i.e. if…

  • AXI Locked Write and Lock Scope

    Hi All,

           1)  1st master is doing locked write transfer to 'X location after that, Can 2nd master initiate a read normal transfer for 'Y address in same slave? . And still unlocked transfer is not initiated by the 1st master?.…

  • ACE - ReadNoSnoop transaction

    In ACE Specifications - ARM IHI 0022E, in ReadNoSnoop transactions how is the following other state of cacheline

    given on page number C4-197 transaction permitted :

    Start State  - ShareClean

    RRESP[3] - 0, RRESP[2] - 0

    End State - Invalid or UniqueCl…

  • AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

  • AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer…

  • In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?

    In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?

  • AMBA3 AXI - Exclusive access

    1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location??

    Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID (first is 00 and second is 01) to the sam an address…

  • AMBA3 AXI Relationship Between Channels

    In the document AMBA3 AXI (3.2 Relationships between the channels)

         Two relationships that must be maintained are:

              • read data must always follow the address to which the data relates…

  • PLEASE HELP ME (AMBA3 AXI)

    1/ WHY "the width of the ID field at a slave interface is wider than the ID field at a master

    interface"??? Can you please explain in more detail the reason???

    2/ Do AXI protocol have support "read interleaving"???

    Thanks you so much…

  • AMBA AHB TRANSFER CONTINUE AFTER ERROR RESPONSE

    Hello everyone,


    Please describe me the transfer continuation process after ERROR response from the slave.ERROR response.jpg

    As shown in the above figure at cycle T4 if MASTER identifies the ERROR response from the SLAVE. Now, if the MASTER wants to continue the current transfer…

  • Please help about AMBA AXI 3.0

    I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0

    1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?

    2. In the FIXED…

  • hi. i wonder AMBA 3.0 AXI difference of data interleaving and write data interleaving

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.



    as you can see the first picture, slave send the read…