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  • hi. i wonder Register Slice of AMBA 3.0 AXI

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    Recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.


    Register slice is described in AMBA 3.0 AXI.

    "This makes…

  • General Feature of Cortex processors on cache coherency

    Hi Experts,

    Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

    I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…

  • TRANSFER CONTINUE AFTER ERROR RESPONSE FROM SLAVE

    Hello everyone,

    I want to understand the transfer continuation process from AHB MASTER during ERROR response from AHB SLAVE.

    As specified in the AMBA Specifications (Rev 2.0) IHI0011A_AMBA_SPEC.pdf section 3.9.4 page no 3-23 :

    3.9.4 Error response

    If a slave…

  • ACE-Lite Master and Slaves

    Hello Ashley,

          I have couple of basic doubts w.r.t ACE-Lite Slave.

          The AMBA spec for ACE-Lite says that " ACE-Lite is used by master components that do not have hardware coherent caches". But they can issue transactions…

  • Problems with  AXI4  write data channel

    Hello:

        Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte  slave0 has…

  • STM(System Trace Macrocell)

    Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?

    what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.

  • Regarding retry response

    Im new to the ahb protocol can  any on give me an idea about retry response, when a retry response is generated from slave side.

  • Burst termination with BUSY transfer on AHB

    I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated.

    But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length burst.

    Doesn't it mean that INCR is not terminated?

    …

  • AHB revisions from AHB3 to AHB5

    I noticed that "Multi slave select" is one of the new features in AHB5.

    But, isn't it possible to set multiple slaves in a system with a decoder and a multiplexor?

    I think we can do that with AHB3.

    What is the major difference between AHB3…

  • AMBA

    How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…

  • APB3 Slave responding when PSEL = 0

    Hello All,

    Here at IP Level verification we have no issues as the Master APB does not latch the PREADY, but at SOC Level with multiple APB Slaves 

    The Master performs some transaction with APB SLAVE 1 and before switching to APB SLAVE 2 , it disables the…

  • AXI4 Lite handshake

    Hi,

    in the AMBA/AXI Protocol specification, I read

    There must be no combinatorial paths between input and output signals on both master and slave interfaces.

    What signals, explicitly, may not have combinatorials between them?

    Thanks in advance.

  • AXI3 write data interleaving with same AWID

    This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple outstanding transactions. But I have a query on…

  • Axi4 Write Transaction

    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.

  • Assertion for Multiple Transfer on APB Bus

    Hi,

       Can you please help me in writing assertions to take care on multiple transfer in APB bus?

    Thanks,

    Rakesh

  • Amba Adaptive Traffic Profiles question

    Hi,

    I see the Amba Adaptive Traffic Profiles blog and it's interesting.

    Is it only a specification ?

    Any public domain source code (C++ or Python) or executable to generate the traffic patterns in a commercial simulator ? 

    Thanks,

    David

  • AMBA Adaptive Traffic Profiles

    The performance requirements of computing systems have been growing rapidly, year on year. Demand is further increased by the many new performance-demanding applications that are emerging across multiple market segments, such as machine learning (ML)…

  • ACE protocol : Eviction and snoop request at same time

    How to handle below scenario ?

    • At time t1 let us suppose L1 data cache is evicting a line and write address is sent on write address channel by asserting AWVALID (AWREADY is high)
    • At same time t1, there is a snoop request from interconnect on snoop address…

  • HRANT assertion and deassertion in combination with HLOCK and HREADY

    Hi,

    Regarding the HGRANT signal have following queries

    1) When Master has requested  for the bus access; arbiter has provided it the grant; When the arbiter can pulls out the HGRANT

        a) For Non-locked transfer: When another master requests for bus access;…

  • Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification

    Hi,

    As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian as BE8. Hence, the active byte lanes for a 32-bit big…

  • boundary concept

    Hi all,

    I am new to protocols AHB and AXI.

    can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?

    Also what these boundaries are for? Does they represent the maximum slave size?

  • Where could I find a good start for studying Memory Types and Attributes as well as Monitors and semaphores ?

    Hi I was studying the memory system ... and I found three related concepts/topics but I couldn't grasphow these concepts are related to each other and to the AMBA Protocol ... these concepts are : - memory Type - memory Attributes - Monitors and semaphores…

  • Transfer size in AMBA AXI

    Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data transfer) is changing in each transfer within a…

  • AXI-4 questions

    Hello,

    I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.

    1) I would like to know how read and write address requests issued…

  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?