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  1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst.

  2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert a last of the burst.

Use case which come to my mind is.

1. Display controller might need to flip an image 180 degrees. Here memory reading pattern is reversed.

2. Where ever there is LIFO (Last In Fist Out) implementations.

Hi All,

                       I am doing single write operation to AXI slave from avalon BFM. The data and address signals

are reached into the axi slave.But if i am try to read back the data which i have written in the same location,the data is  not matched.

It…

Is interleave and reorder the same concept?

My interpretation is a slave can reorder without interleaving, which means entire read burst are reordered with no interleaving. So my understanding is they are different. Confirm my understanding.

why we need write strobe signal in axi where we generate in our verif env

Thanks

Hi,

Can any one explain me how address decoding is done in amba ahb?

HRESP  is given  for address or data??

hi,

Is HREADY is used by the slave  to notify the master that it is ready to receive or to indicate transfer is completed??

thanks in advance

Could you please help me on this topics in AXI4 protocal ::

1. what is meant by Aligned and Unaligned address?

2.How can I calculate WRAP boundary calculation in AXI4? please explain with example?

what happen if WVALID asserted before AWVALID ??

In case of AXI4 lite protocol,whether BValid should be asserted before WVALID signal deassertion? what is the legal case?

In specification it is mentioned that WREADY signal can wait for AWVALID and WVALID signals.

Does it mean that WREADY signal should be asserted only after assertion of AWVALID and WVALID signals.

What is the relation between these signals?

and performance…

Hi All,

                           I have doubt in ahb_lite hresp signaling when the address phase is extending.

In the following diagram transfer address c is extending because of data phase of B.

In 3rd clk cycle address C is sampled so that shall we expect the…

Hi,

In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)…

Hi All ,

                      The following figure shows the INCR4 burst transaction.

Here the address increment is happening in each clk cycle  As per AHB protocol Single outstanding address is allowed.

What are the possible adjustment has to be made for this transaction…

Difference between axi_4 and axi4_alite?

Hi All ,

            Can anyone please tell the difference btw AXI3 and AXI4.

Regards

Muthuvenkatesh

what are the possible values of strobe for a half word transfer in AXI4 lite? 

Are these following values on WSTRB valid ?

-1001

-0101

-1010

hi,

what are the purpose of interconnect..?and why we nedd address routing table..in axi4

Hi,

 I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?

1.I can think of invalid address as the only case. Is there any other scenario?

2. I am performing a INCR4 transfer on AHB side…

Hi,

I am creating a systemC model for a peripheral which has an AXI4 interface.

Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?

Is it available from ARM, a ThirdParty vendor, or the opensource community?

Hello I want to know the calculation for

HSIZE=2 and Wrap 8

and starting address is 0x4

and how we are doing alignment ???

I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

Eg. Burst length- Two , Burst size 16 bytes.

Please give me answers for different types of data bus width say for bus width …