Browse By Tags

  • Bus Matrix

    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?

  • ARM Cortex ICode, DCode, System buses

    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
    …

  • Where could I find a good start for studying Memory Types and Attributes as well as Monitors and semaphores ?

    Hi I was studying the memory system ... and I found three related concepts/topics but I couldn't grasphow these concepts are related to each other and to the AMBA Protocol ... these concepts are : - memory Type - memory Attributes - Monitors and semaphores…

  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

  • DesignStart Pro: APB on FPGA via Quartus Prime

    Hello,

    I try to implement the Cortex-M3 processor on an FPGA via Quartus Prime. I set up the SSE050 Subsystem and tried to connect several peripherals to the board. I want to test the functionality with a uVision project lighting some LEDs. To have access…