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  • How to map tag RAM banks to data cache lines in Cortex-R5?

    Hi,

    We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

  • Problems about signal dependencies in AXI spec

    Hi,

    In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

    My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

  • AXI read response in error case

    Hi,

    In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

    Now my question here is if the response is going to be ERROR(lets say SLVERR…

  • Why AXI4 changed the definition of AxCACHE?

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

  • Store operations where the cache line is already cached (ACE protocol)

    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

    The initiating master component requests a unique copy of the cache line…

  • Removal of WID's in AMBA AXI4

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

  • Xen/dom0 on Juno

    Hey all,

    I have been playing around with Xen and Dom0 on a Juno r0 board. Currently dom0 is failing to initailize USB. This is an issue because the rootfs depends on the usb.

    usb 1-1: new high-speed USB device number 2 using ehci-platform

    usb 1-1: device…

  • AMBA Protocols (Specially AXI) frequency limit ?

    I wanted to ask about AMBA Protocols (Specially AXI) frequency limit ? Is there any upper limit for AXI4 of maximum operating frequency ? what is it ?

  • Partial Word Access to Altera Avalon Memory-Mapped Slave

    when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

    Background:

    In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

    I am responsible for the board and FPGA design. Another software…

  • why there is no split or retry responce in AXI ?

    In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?

  • AXI narrow read with unaligned address

    Hi,

    I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario:

    - 32 bit data bus

    - address x0001

    - length 0 (1 beat)

    - size 1 (2 byte)

    My interpretation of the spec is that in…

  • RMW operation on SRAM via AXI

    I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?

    Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…

  • AXI handshake between AW/AR-READY and B/R-RESP

    In AXI Write how the handshake between AW channel and B channel is taken care.

    Standard says that 

    "the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"

    Does that means BVALID will never be asserted in the same…

  • How does QoS with priority and ordering allowed with AXI ID?

    I have one question for QoS with AXI4:

    Can one master have multiple QoS values?

    Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

  • ARM AXI4 protocol assertions trigger errm_wdata_num_prop5 and errm_wlast_stable quesitons

    Hi,

    I'm getting two AXI4 protocol assertion errors.

    For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

    The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

    Is this a…

  • AXI modifiable read access

    The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

    "a read transaction can fetch more data than required"

    To me, this can be interpreted in two ways:

    1. The RVALID signal of the slave can be asserted for…

  • Project on AXI Bus.

    Hi,

    I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work? 

  • unaligned address in AXI protocol

    i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…

  • Further explanation needed for VAxQOSACCEPT, AWAKEUP, ACWAKEUP and SYSO*

    Hi ARM/arktos,

    Seems like this online discussion is not working properly.

    I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.

    So most likely you may not see it.

    Below is my reply to your answer to my…

  • AXI4

    In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this?  What is the meaning of bandwidth in this context? What are the  values of bandwidth and frequency? How they decide the operating…

  • AXI3 locked access

    I want to know what happens in these scenarios :
    1) Assume Master1 (M1) is doing locked access, if locked access fails before M1 does unlocking transaction what is the response to the M1?
    2) Assume M1 is doing locked transaction, if other Master2 (M2)…

  • AXI Burst Size meaning

    Dear Community,

    I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction.

    a)
    I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.
    When there are Bust…

  • Does CHI protocol interface use pipelines or register slice to support long distance connections ?

    Hi,

    I assume CHI needs to either pipeline or implement something like the AXI register slice to support long distance connections.

    Please confirm and where can I find relevant information for this topic.

    Thanks,

    David

  • AXI AHB APB quick reference cheat sheet

    Hi,

     I have tried to find a quick reference for AXI, AHB & APB to no avail, and after having to flit between the various documents and tables, I eventually created my own.

    So not sure of the legal ramifications of posting this elsewhere and whether…

  • AMBA AXI reset

    According to spec IHI0022D_amba_axi_protocol_spec  section A2.1 page number: A2-28

            "All signals are sampled on the rising edge of the global clock "

         Q) Should RESET_N also  be sampled on the rising edge only?

    Section A3.1.2,  says

       "The AXI protocol…