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  • MakeUnique Transaction (ACE protocol)

    Hi.,

    As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…

  • Are there any restrictions for the width of an address signal in an AXI4 interface?

    Hello,

    in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate…

  • Need info AXI4- AxPROT

    Hello Everyone,

    Can someone explain the use cases of AxPROT? I am not fully clear on how to use these bits in a system. (So i would like to hear some use cases for this port)

    Also, Please provide some info on how to set AxPROT[1] (How the system will distinguish…

  • Address decoding in AXI4 interconnect

    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done.

  • In read or write transaction in AXI.what happen if data transaction  is before address.

    HI there,

    I have question regarding transaction in AXI4 bus (or any other bus). What happens  in write any read action when data transaction (handshaking) occurs before  address  transaction (handshaking) ?

    Will the data be written to the…

  • Does an AXI4 master have to assert the correct WSTRB for unaligned transfers?

    Take the unaligned transfer on page A3-55 in the "AMBA AXI and ACE Protocol Specification" with address 0x07 as example.

    Bus width and data transfer width should be both 32 bits. First write should be to address 0x07. This would lead to bytes…

  • AXI4 - read data interleaving

    Hi Folks,

    We need a clarification on Read Data Interleaving on AXI4

    Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:

    Multiple Read commands can be executed simultaneously and data interleaving is supported…

  • Cortex-M7: Winner of Analysts’ Choice - Best Processor IP

    We are delighted to announce that the ARM Cortex-M7 processor has been selected by the Linley Group as the “Best Processor IP” for 2014.



    Linley Group Analysts Choice Logo.png

    Each year The Linley Group (one of the leading semiconductor analysts) presents its “Analysts’ Choice…