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  • Write Data Interleaving - AXI

    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    Hello,

    Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
    [Chapter 8.5  Write data interleaving]

    "The order…

  • AXI4 Lite handshake

    Hi,

    in the AMBA/AXI Protocol specification, I read

    There must be no combinatorial paths between input and output signals on both master and slave interfaces.

    What signals, explicitly, may not have combinatorials between them?

    Thanks in advance.

  • How to map tag RAM banks to data cache lines in Cortex-R5?

    Hi,

    We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

  • Problems about signal dependencies in AXI spec

    Hi,

    In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

    My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

  • AXI read response in error case

    Hi,

    In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

    Now my question here is if the response is going to be ERROR(lets say SLVERR…

  • Why AXI4 changed the definition of AxCACHE?

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

  • Store operations where the cache line is already cached (ACE protocol)

    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

    The initiating master component requests a unique copy of the cache line…

  • Removal of WID's in AMBA AXI4

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

  • AXI4 - read data interleaving

    Hi Folks,

    We need a clarification on Read Data Interleaving on AXI4

    Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:

    Multiple Read commands can be executed simultaneously and data interleaving is supported…

  • Xen/dom0 on Juno

    Hey all,

    I have been playing around with Xen and Dom0 on a Juno r0 board. Currently dom0 is failing to initailize USB. This is an issue because the rootfs depends on the usb.

    usb 1-1: new high-speed USB device number 2 using ehci-platform

    usb 1-1: device…

  • Why does AHB or APB support only 16 slave devices?

    I would like to know why only 16 slave device select lines are present in the AHB and APB bus architectures.

  • what are these axi transaction types mean? fixed, incremental, wrapped, reversed? Are there any docs descriped them in detail?

    As the title says..

  • AXI

    What is byte lane in AXI?

  • read transfers

    In read transfres how the slave indicates the transaction is over?

  • AXI read transfer

    If the slave is not able to process read request from master, which response is expected from slave?

  • AXI

    Why burst must not cross 4kb  in AXI ?

  • Working frequency on AMBA- APB,AHB, AXI

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

  • axi read transfers

    what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

  • 4k boundary in AXI

    Why the word boundary in AXI is 4k?

  • AXI transfer

    Consider Data interface is 64 bit.
    It is Write transfer.
    AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.

    Scenario 1:
    Burst -> Address:0, size:3, length:1, burst_type…

  • Why do AMBA AXI does not support AxBURST of decrementing address type?

    Use case which come to my mind is.

    1. Display controller might need to flip an image 180 degrees. Here memory reading pattern is reversed.

    2. Where ever there is LIFO (Last In Fist Out) implementations.

  • AXI WRITE DATA CHANNEL

    Hi All,

                           I am doing single write operation to AXI slave from avalon BFM. The data and address signals

    are reached into the axi slave.But if i am try to read back the data which i have written in the same location,the data is  not matched.

    It…

  • AXI read reordering depth and read interleaving depth. Are they same?AXI

    Is interleave and reorder the same concept?

    My interpretation is a slave can reorder without interleaving, which means entire read burst are reordered with no interleaving. So my understanding is they are different. Confirm my understanding.

  • why we need write strobe in axi

    why we need write strobe signal in axi where we generate in our verif env

    Thanks

  • AXI WVALID before AWVALID

    what happen if WVALID asserted before AWVALID ??