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  • AHB revisions from AHB3 to AHB5

    I noticed that "Multi slave select" is one of the new features in AHB5.

    But, isn't it possible to set multiple slaves in a system with a decoder and a multiplexor?

    I think we can do that with AHB3.

    What is the major difference between AHB3…

  • Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification

    Hi,

    As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian as BE8. Hence, the active byte lanes for a 32-bit big…

  • boundary concept

    Hi all,

    I am new to protocols AHB and AXI.

    can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?

    Also what these boundaries are for? Does they represent the maximum slave size?

  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

  • HREADY when no activity on bus

    Hello,

    We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

    ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

    So the questions…

  • AHB Slave HREADY

    Hello

    I am new to AMBA and I am writing code AHB slave in one of my project, I have read specs.

    My question is Is there any specific condition for slave when it gives HREADY low?

    I am confused with HREADY signal that it is provided by the slave but at which…

  • AHB

    Hello,

    1.) Is it possible in real system that Master will send start address 0x01 ?

    If Master wants to write only one byte at address 'h1, other addresses what ever value it has then how Master will give request?

    HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST…

  • why there is no split or retry responce in AXI ?

    In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?

  • MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave

    Hi,

    Facing the issue:
    "MBERROR :  AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave"

    Here is the Inputs:

    We are using the custom SOC, in which we are testing the CLCD controller(IP ARM PL111)
    connected…

  • AHB protocol

    I am newly learning AHBprotocol  i just want to know what is meaning of single cycle bus master handover?

  • Why does AHB or APB support only 16 slave devices?

    I would like to know why only 16 slave device select lines are present in the AHB and APB bus architectures.

  • AHB wait state insertion

      1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst.

      2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert a last of the burst.

  • AMBA AHB

    Hi,

    Can any one explain me how address decoding is done in amba ahb?

  • HRESP

    HRESP  is given  for address or data??

  • amba ahb

    hi,

    Is HREADY is used by the slave  to notify the master that it is ready to receive or to indicate transfer is completed??

    thanks in advance

  • Relation between Hsel and Hready in AMBA AHB

    Hi,

    In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)…

  • AHB_LITE Extended address phase

    Hi All ,

                          The following figure shows the INCR4 burst transaction.

    Here the address increment is happening in each clk cycle  As per AHB protocol Single outstanding address is allowed.

    What are the possible adjustment has to be made for this transaction…

  • Error scenario in AHB protocol

    Hi,

     I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?

    1.I can think of invalid address as the only case. Is there any other scenario?

    2. I am performing a INCR4 transfer on AHB side…

  • Narrow burst (32 bit read) on a 64 bit data bus AXI read transaction

    Hello All,

      I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address.

    When  I read back at the same address, I am getting as 2 64 bit data each for 2 clock cycles. Why is this?

    Scenario : Single…

  • Alignment Address Calculation in AHB

    Hello I want to know the calculation for

    HSIZE=2 and Wrap 8

    and starting address is 0x4

    and how we are doing alignment ???

  • Working frequency on AMBA- APB,AHB, AXI

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

  • AHB slave

    1.) In AHB, When early burst termination is occurred, HRESP should be OKAY and HREADY should be high?

    2.) Is there any possibilities that if write transaction is in progress and if burst is not completed then HWRITE will be low after some clock. i.e. if…

  • Is there a limit on the number of APB slaves on the AHB to APB bridge?

    Is there a limit on the number of APB slaves on the AHB to APB bridge?

  • Question on duration of hsel in AHB

    Hi,

    My question is about duration of hsel in AHB. While performing a write operation to a particular slave, if hsel for the slave is asserted (hsel=1) in the address
    face and is deasserted (hsel=0) in the data phase, will it guarantee that data is written…

  • New AMBA Specification Extends Security to Embedded Design: AMBA 5 AHB5

    The amount of data we generate is growing exponentially. Gartner has predicted that in 2015 the global mobile data traffic will be a total of 52 billion terabytes, an increase of 59 percent on 2014. It’s a staggering number that is driven not just by…