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Hello,

We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

So the questions…

Hii,

Greetings !!

I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

Please someone help me out.

Thanks in advance

Regards

Ujjwal

  1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst.

  2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert a last of the burst.

Hi,

Can any one explain me how address decoding is done in amba ahb?

HRESP  is given  for address or data??

hi,

Is HREADY is used by the slave  to notify the master that it is ready to receive or to indicate transfer is completed??

thanks in advance

Hi,

In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)…

Hi All ,

                      The following figure shows the INCR4 burst transaction.

Here the address increment is happening in each clk cycle  As per AHB protocol Single outstanding address is allowed.

What are the possible adjustment has to be made for this transaction…

Hi,

 I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?

1.I can think of invalid address as the only case. Is there any other scenario?

2. I am performing a INCR4 transfer on AHB side…

Hello I want to know the calculation for

HSIZE=2 and Wrap 8

and starting address is 0x4

and how we are doing alignment ???