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  • Simplifying workload modeling with AMBA ATP Engine

    We are pleased to announce the release of the AMBA ATP Engine, an open-source implementation of AMBA ATP (Adaptive Traffic Profiles). The Engine significantly simplifies the adoption of AMBA ATP for workload modeling and accelerates the research and development…

  • AMBA AHB

    1)what is the difference between HLOCK and HMASTLOCK in AMBA AHB?

  • AMBA AHB

    1)according specification The SPLIT and RETRY responses provide a mechanism for slaves to release the bus when they are unable to supply data for a transfer immediately.when the slave issue SPLIT?when slave issue RETRY?is there any specific condition is…

  • [APB] Assert timing of PSTRB and PPROT

    Hi All,

    I have a question about assert timing of PSTRB and PPROT.

    I think APB4 spec (IHI0024C_amba_apb_protocol_spec.pdf) does not describe when PSTRB and PPROT should be asserted.
    I guess these signals should be asserted while PSEL is high like PADDR…

  • [APB] Assert timing of PSTRB and PPROT

    Hi All,

    I have a question about assert timing of PSTRB and PPROT.

    I think APB4 spec (IHI0024C_amba_apb_protocol_spec.pdf) does not describe when PSTRB and PPROT should be asserted.
    I guess these signals should be asserted while PSEL is high like PADDR…

  • AMBA

    1)AMBA protocols have any modes,like simplex,full duplex or half duplex?

  • Getting started with AMBA and AMBA AXI

    As you may be aware, far from being a misspelled fossilized tree resin, AMBA is a freely available open standard for the connection and management of functional blocks in a system-on-chip (SoC). Since the mid-90s, AMBA has been implemented by vendors…

  • Readunique and cleanunique transactions in ACE protocol

    In case of readunique transaction cache line is copied into the initiating master's cache(whether it is clean or dirty) and invalidated in snooped master's cache and then store operaation is performed in initiating master's cache line.

    In…

  • AMBA AXI

    What is use of AWPROT and ARPROT signal in AXI? I meant the scenario where exactly it is used?

  • AMBA AXI Write response

    I am just going through the specs of AMBA AXI.
    I've few questions.It will be great if anybody clarify
    1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
    2) How to terminate…

  • applications of amba axi

    Note: This was originally posted on 7th February 2007 at http://forums.arm.com

    hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used in the real time applications or some specific devices…

  • AXI write strobes

    Note: This was originally posted on 21st February 2007 at http://forums.arm.com

    the AXI spec says:

    10.1 About unaligned transfers
    [...]
    For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be…

  • Basics: C programming for ARM - AHB transfers

    Note: This was originally posted on 18th September 2007 at http://forums.arm.com

    Hello,
    Would someone please help me about the next basic things?
    I have programed microcontrollers in the past but now I need to work with ARM processors and need some basic…

  • AXI Read/Write ordering

    Note: This was originally posted on 24th October 2007 at http://forums.arm.com

    Hello,
       Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them.  It then says that if a RAW dependency exists, the master must wait…

  • More AXI write/read ordering

    Note: This was originally posted on 25th October 2007 at http://forums.arm.com

    In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address.  Sounds like the master's assumption upon…

  • AXI Cacheable vs. Bufferable

    Note: This was originally posted on 19th November 2007 at http://forums.arm.com

    If an AXI slave acting as a bridge has accepted a bufferable (ACACHE[0]) and cacheable (ACACHE[1]) write and responded with BRESP, is it required to flush this buffered write…

  • How to go from 32-bit to 64-bit AHB data bus

    Note: This was originally posted on 21st November 2007 at http://forums.arm.com

    Hi,
    I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked…

  • AXI protocol

    Note: This was originally posted on 30th December 2007 at http://forums.arm.com

    Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving  in detail...as i`m very confused with these terms

  • Confusion over AMBA AHB hsize[] signal definition

    Note: This was originally posted on 26th February 2008 at http://forums.arm.com

    After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface.  If an AHB bus is implemented…

  • AHB Multilayer

    Note: This was originally posted on 30th April 2008 at http://forums.arm.com

    In the multilayer environment,  i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic…

  • AXI locked access

    Note: This was originally posted on 29th May 2008 at http://forums.arm.com

    Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel…

  • AHB WRAP address boundaries

    Note: This was originally posted on 18th June 2008 at http://forums.arm.com

    AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same for each WRAP4, WRAP8, and WRAP16 cases? Or, should…

  • Wrap address usage?

    Note: This was originally posted on 18th October 2008 at http://forums.arm.com

    Hello guys..

    I am working on AMBA AHB...
    and came across the wrap address term...
    Can you tell me that which kind of application need to do transfer using wrap address?

  • questions about APB advantages

    Note: This was originally posted on 8th November 2008 at http://forums.arm.com

    Hi! dear all  :lol:
    Some APB advantages are listed in AMBA 2.0 spec. They are

    "¢ performance is improved at high-frequency operation
    "¢ performance is independent of…

  • AHB Arbiter

    Note: This was originally posted on 21st November 2008 at http://forums.arm.com

    Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?