Is it possible for a CHI Node to receive an L-Credit Return when in RUN State?
Hi All,
I have a question on AMBA5 AHB feature : Stable_between_Clock property
The AMBA5 AHB Specification describes:
Signals that are described as being stable are required to remain at the same value when sampled at different rising clock edges in an…
In AHB5, we have extended memory bits as [6:4] hprot. Previously we have [3:0] hprot. For implementation purpose, i treated [6:4] as a separate signal. This separate signal am qualifying based on some filter, just because not to consider for older AHB…
Hello,
i didnt find at spec any note about the waited write transfer.
for example
T1 : NONSEQ + write transfer + HREADY is high
T2: HREADY dropped + HTRANS is idle - HWDATA ?
does the HWDATA have to be the right data or it can be any junk ? and only when…
1. How barrier instructions like `dmb ishld` and `ldar/stlr` translate to ACE barrier transactions?
I am curious about how barrier instructions which will only affect specific types of memory operations would translate to ACE barrier transactions.
I supposed…
The performance requirements of computing systems have been growing rapidly, year on year. Demand is further increased by the many new performance-demanding applications that are emerging across multiple market segments, such as machine learning (ML)…
Hi,
As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian as BE8. Hence, the active byte lanes for a 32-bit big…
Hello to all,
I have a question about AMBA3 AHB-Lite and AHB5 Specification:
In AMBA3 AHB-Lite Specification, "Table 6-2 Active byte lanes for a 32-bit big-endian data bus" is mean word-invariant big-endian or byte-invariant big-endian? Why its…
Hi all~
I have some questions about AHB5 specification
1.If CPU(or another slave) is in 32-bit single-copy atomic group, can I only write/read a byte to it ? (HWDATA/HRDATA is 32bit-width, HBUST=SINGLE, HSIZE='b000)
2.What is the description "…
Can somebody please explain how barrier transactions in ACE work?
Thanks in advance.
The AMBA5 spec for ACE5 shows some new signals versus ACE4 :
VAWQOSACCEPT
VARQOSACCEPT
AWAKEUP
ACWAKEUP
SYSCOREQ
SYSCOACK
How are these used in an SOC system ?
For example, I think but I'm not usre if VAWQOSACCEPT, VARQOSACCEPT is output by each slave…
Hi ARM/arktos,
Seems like this online discussion is not working properly.
I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.
So most likely you may not see it.
Below is my reply to your answer to my…
I have doubt in ahb_lite hresp signaling when the address phase is extending.
In the following diagram transfer address c is extending because of data phase of B.
In 3rd clk cycle address C is sampled so that shall we expect the…
In late 2014, Carbon released the first Carbon Performance Analysis Kit (CPAK) utilizing the ARM CoreLink CCN-504 Cache Coherent Network. Today, the CCN-504 can be built on Carbon IP Exchange with a wide range of configuration options. There are now…
Through a blog post by Jeff Defilippi, Arm has just announced the new Arm AMBA 5 AXI5, ACE5 and ACE5-Lite protocols; you can request the the latest AMBA 5 specs through a link in that blog. These protocols are employed by Arm's latest technology, including…
Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols have been implemented in Arm’s latest technology…
I already shared last month some details of work we have been doing with Arm on an HPC testchip, the good news continues with our announcement of extended support for the AMBA 5 protocol family with support for CHI.b in our Cycle-accurate performance…
Can I get reference document for AMBA 5 CHI specification.? Please Can anyone share me that doc...?
Thanks & Regards,
Rakesh Reddy.B