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  • AMBA AHB5 : Stable Between Clock Question

    Hi All,

    I have a question on AMBA5 AHB feature : Stable_between_Clock property

    The AMBA5 AHB Specification describes:

    Signals that are described as being stable are required to remain at the same value when sampled at different rising clock edges in an…

  • About AHB5 protection control signals

    In AHB5, we have extended memory bits as [6:4] hprot. Previously we have [3:0] hprot. For implementation purpose, i treated [6:4] as a separate signal. This separate signal am qualifying based on some filter, just because not to consider for older AHB…

  • AHB amba 5 lite - waited write transfer

    Hello,

    i didnt find at spec any note about the waited write transfer.

    for example 

    T1 : NONSEQ + write transfer  + HREADY is high

    T2: HREADY dropped + HTRANS is idle - HWDATA ?

    does the HWDATA have to be the right data or it can be any junk ? and only when…

  • Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification

    Hi,

    As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian as BE8. Hence, the active byte lanes for a 32-bit big…

  • single-copy atomicity question for AHB5

    Hi all~

    I have some questions about AHB5 specification

    1.If CPU(or another slave) is in 32-bit single-copy atomic group, can I only write/read a byte to it ? (HWDATA/HRDATA is 32bit-width, HBUST=SINGLE, HSIZE='b000)

    2.What is the description "…