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Hi,

Can someone clarify below queries I have wrt AHB-Lite,

1. Is there any relation between HTRANS=IDLE and hready ? Like,
   1. Whenever IDLE comes hready is de-asserted (or)
   2. Whenever hready is de-asserted, master gives IDLE
2. What is the maximum duration…

In AHB-Lite cases, every transfer starts with address phase with signals from master.

And also in multi-master cases, arbiter decides with whether it can GRANT bus access to other masters or not.

So, I think it's fine to only let masters or arbiters to…

Hi,

In spec it's mentioned that in WRAP transaction the un-aligned address will be made aligned but only when it's crossing the boundary.

Wanted to know what's expected when the WRAP txn is started with a un-aligned address.

Case1: Starting…

I've understood how it works and what happens in it, but  what is the use of having a wrapping bursts? What are some scenarios where it provides an edge?

This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and where exactly is it incorporated(inside the processor…

Currently, the processor has simple load store architecture and is directly connected to the external memory without any bus interface. For the sake of uniformity, I'm implementing the AHB-Lite Bus Architecture for this system. The processor by design…

I am not able to see any visible improvements due to the BURST transfers. The same BURST transfer could be done through multiple SINGLE transfers, in the same number of cycles. Then what is te advantage of having BURST transfers?

HI 

     I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not.

    If i am using a write based read ,The write is not complete due to wait at the time ,At the time again i put a same addr in read transfer…

Hi All ,

                      The following figure shows the INCR4 burst transaction.

Here the address increment is happening in each clk cycle  As per AHB protocol Single outstanding address is allowed.

What are the possible adjustment has to be made for this transaction…

Hi,

 I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?

1.I can think of invalid address as the only case. Is there any other scenario?

2. I am performing a INCR4 transfer on AHB side…