I am converting a board from an 80C32 to a P89C51RC2Hxx. This board has SRAM mapped at 0x8000 - 0xFFFF and I/O mapped at various places from 0x0000 - 0x0700 and declared as XDATA. The decode for the I/O was done with a PAL and used PSEN and a few address lines to differentiate between the SRAM (XDATA) and the I/O. The problem is that my I/O will not work with this uP but my SRAM is fine. When I look at it with a logic analyzer SRAM select is firing every time I try to write to the I/O. I have tried every type of mapping combination but it doesn't change. It works fine with my emulator but no when on the chip. Any ideas would be greatly appreciated. Steve
1) The RC2H according to my Philips FAE is ther "prototype" of the RC2, make sure you specify the current version. 2)"The decode for the I/O was done with a PAL and used PSEN and a few address lines to differentiate between the SRAM (XDATA) and the I/O." Are you running with the same crystal ? are you running the RC2 in 12 or 6 clock mode? either having changed would make your I/O timing different and could very well be the source of your problem. Erik
It turns out the problem was that some of my I/O was mapped in the address space of the ERAM. The Keil compiler has a check box that allows you to use on-chip xram, but if not selected it does not disable this feature. To disable you must set AUXR register on boot up allowing the 89C51RC uP to act like a traditional 8051. Steve