Immediate offset problem with the LDR commands

Find out and think about the differences between these two instructions below and what a two pass assembler is faced with in the two situations above.

LDRB.N  R0,[R1,#USB0_CSRL0]
LDRB.W  R0,[R1,#USB0_CSRL0]

@Per Westermark

My processor is CM3. Limits of Immediate ofset mode of the LDR command are -255 to 4095.

Therefore i think Keil assembler gives a wrong error message.

I know the differences of .N and .W suffix. Limits of the immediate offset of the cortex m3 LDR command can not be between the 0x00 and 0x1F. Therefore assembler gives wrong error.

Assembler and/or compiler not importand details for my main question.

You don't know that. You have no idea what's important for your main question and what isn't.

Else you cant see and you cant understand the niceties in my questions.

There are no "niceties" to be found in any of the pointless repetitions of your question. Just the obnoxiousness of a person who asks a question, then is so sure he knows the answer better than the people he asked, that he considers himself qualified to dismiss answers as unhelpful without so much as pretending to consider them first.

You don't want any help, fine --- so stop wasting everybody's time by pretending to ask for it.

I found the answer for my first question and i wrote it. This is an assembler's problem and i think at the next versions Keil repairs.

If you look at the answers to my question unrelated ordinary conceivable that you will see the answers.

I'm not coming here to chat or controversy. I'm coming to find a single reply of my question I was just right.

At the same time the problem is only missing my Ingilizce Caused by.

I found the answer for my first question and i wrote it.

So you believe. Just about everybody, up to and including the company that designed both the CPU and the assembler you're using, disagrees with you on that count.

I'm coming to find a single reply of my question I was just right.

Well, this is a discussion forum, not a "I believe you" automaton. We're people, not Electric Monks (courtesy Douglas Adams).

In other words: if you can't stand the heat, stay out of the kitchen.

This place is technical forum. You're not going to social sciences forums, why?

(Let wait the new version of assembler compilers)

Go away, please. Enough is enough!

Did you see anything about "Some or all forms of this instruction are 16-bit (narrow) instructions in Thumb-2 code. For details see [...]"?

... I already tried pushing him in this direction with no success...!

(These are the narrow and wide variants that he claims to understand the implication of)

LDRB.N  R0,[R1,#USB0_CSRL0]
LDRB.W  R0,[R1,#USB0_CSRL0]

Yes, but the OP is convinced that we still haven't even understood his problem, so why would he assume that any of our comments may be related to the problem?

Continuing on Andys track: a C programmer would have managed to implement quite a lot of real functionality by now since the C compiler condenses quite a lot of experience and documentation into a readily available digital servant.

> This is an assembler's problem and i think at the next versions Keil repairs.

I can see that the observed behavior might appear to be a bug, especially after spending ours getting down to the root cause of this. However, this is arguably not a bug since the behavior is documented. See here:
infocenter.arm.com/.../armasm_cihdgigd.htm

An action item for ARM could be to improve the error message so that it at least mention the possibility of a "wrong" instruction size.

Regards
Marcus
http://www.doulos.com/arm/

This place is technical forum.

More to the point, it's a dicsussion forum. You don't seem to know what that means, though. You come here not just expecting, but outright demanding that everybody agrees with you, simply because you say so. That's not discussion, that's attempted dictature.

And since the subject matter of this forum is of a technical nature, you come across people who don't just hold opinions, but actually know things for a fact.

(Let wait the new version of assembler compilers)

Let's, indeed. If only you would shut up til then, we'ld all be better off: you'll be indulging in your own self-righteousness, and we'll be enjoying your silence.

Thank you for providing focused answer to my question. Other friends tried with me not to question.

I want to explain why i think assembler has a bug.

Please carefully follow the next lines.

USB_BASE   EQU 0x40050000
USB0_CSRL0 EQU 0x102

    LDR   R1,=USB_BASE
    LDRB  R0,[R1,#USB0_CSRL0] ; No error !!!!

LDRB R0,[R1,#USB0_CSRL0] means R0 = [R1 + 0x102] (Assmebler compile without error.)

Can I ask, is 0x102 offset value bigger than 0x1F ? Answer is yes.

Why does not give assembler the error messages. (A1174E: "Data transfer offset 0x00000102 out of range. Permitted values are 0x00..0x1F")

Answer: Because 0x102 legal value. Because offset value range of LDR command of Arm Cortex m3 processor is larger than 0x1F. (You may look to any CM3 book).But assembler claims to the contrary.

Let forget this.

Now;

Remove the first two-line and move to the end of the program.(as follows)

    LDR   R1,=USB_BASE
    LDRB  R0,[R1,#USB0_CSRL0] ; Error code is A1174E !!!!

USB_BASE   EQU 0x40050000
USB0_CSRL0 EQU 0x102

Let recompile.

Now assembler will give error messges.(A1174E: "Data transfer offset 0x00000102 out of range. Permitted values are 0x00..0x1F")

What happen and why assembler give this error? Did i changed the offset value? No, this value is not changed and it is 0x102.

Therefore assembler has a bug.

Answer: Because 0x102 legal value. Because offset value range of LDR command of Arm Cortex m3 processor is larger than 0x1F. (You may look to any CM3 book).But assembler claims to the contrary.

Let forget this.

Let’s not forget it.

The LDR and LDRB are different instructions.
From the Cortex-M3 Technical Reference Manual, there are two forms of this particular instruction with immediate offset.

Load memory byte [7:0] from register address + 5-bit immediate offset LDRB <Rd>, [<Rn>, #<immed_5>]
Memory byte [7:0] from base register address + immediate 12-bit offset LDRB.W <Rxf>, [<Rn>, #<offset_12>]

Marcus has provided the link which describes which one is chosen when the assembler does not know the offset in advance or the .N or .W suffix is specified.

infocenter.arm.com/.../armasm_cihdgigd.htm

For forward references, LDR, ADR, and B without .W always generate a 16-bit instruction, even if that results in failure for a target that could be reached using a 32-bit instruction.

This implies the 5-bit immediate offset LDRB variant => 0x1F is the maximum offset.

Why is this difficult to understand?