It's time to do some work on you're compiler. It generates the same code it did 20 years ago. I have to do tricks, instead of writing normal portable code, to get it to generate good code or just use inline assembler. This of course is nothing new, I've been telling you this for almost a decade. Keep in mind that all Intel processors are little endian and that you're compiler generates big endian code, why? You should at least offer a compiler switch to select endianness. Why don't you support C++ and MISRA? Oh and BTW IAR does all of the above TODAY! So clearly they haven't been standing still. (Notice who wrote the paper.)
www.eetimes.com/.../The-Inefficiency-of-C--Fact-or-Fiction-
If you want optimum code out of Keil you don't have a choice but to deal with DPTR.
I asked for a demonstration of necessity of two things, and you answer with a vague claim regarding only one of them. why even bother? Is it really that hard to just admit that you're wrong?
I'll repeat: DPTR is not little-endian in any meaningful way. There's nothing you can do with DPH and DPL that would change in any way if their locations were exchanged --- or, for that matter, if they were moved to completely random locations each.
Is this forum only read by people that work for the company and are set in their ways against listening to customers?
You really need to get help. Your paranoia is getting way out of hand.
My point is why pay for maintance
Oh, for Pete's sake. So don't pay and do us all a favour and get lost, why don't you?
The real answer is simple. YOU have a choice. If YOU don't like it, then YOU don't need to use it.
That's a burry your head in the sand answer. Not everyone does. Some the decision is made for them before they even work for their company. Others are limited by budgets. And still others have to use the tools that the chip manufacture has partnered with.
... there is no such thing as portable code
I wouldn't be fond of that idea but I use the same code on an 8051 and on Windows.
"That's a burry your head in the sand answer."
Not at all. I've faced similar(ish) situations in the past (but stress not concerning Keil) and I always have the ultmiate choice; i.e., find another employer.
If your opinion is that the endian-ness is so critical in the 8051 architecture, then it suggests to me that you've gained little real experience in your 25+ years.
It is up to the developer to fully understand the tools, how they are used and (very importantly) how to use them effectively. If you can't effectively work around such a limitation then it says far more about your abilities that it does the Keil compiler.
It's really a matter of convenience and cost. Having to byte swap because of a lack of compiler switch means extra code space, slower execution and is a maintenance issue.
"Having to byte swap because of a lack of compiler switch means extra code space, slower execution and ..."
That depends entirely on the optimization capabilities of the compiler.
Do you really remember the level of optimization of the first Keil C compiler? I do; it was close to zero and very likely to produce faulty code. Compare that with the current release.
And you said at the very start:
"It generates the same code it did 20 years ago."
That is so not the case. I still have a copy of 3.05 (circa 1990) if anyone wants to see a comparison of produced code, but have long since thrown out all my copies if error reports I sent to Keil.
"... and is a maintenance issue."
Surely someone who writes portable code should be capable of looking after such issues as a matter of course.
If you're going to come out with such confrontational statements then you really should make sure you are factually correct.
Byte suddenly being little or big-endian? Impossible.
The bits in a byte are just that - bits. Don't spend too much time figuring out the bit addressing, thinking that would have anything to do with the little/big endian issue.
Almost all processors defines bytes/words/... to have bit 0 as least significant bit. Creating a bit-addressing instruction, it would be very stupid to suddenly number the bits: 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 ... just to make a statement about big/little order.
But if you do want to have fun - look at some Freescale processors where the bits are numbered in reverse order. Truly magnificent to read a schematic and figure out that A30 is not a really "big" address line but one of the smallest. These bit issues probably resulted from some people stupidly trying to extrapolate word endianness into the naming of individual bits too.
I don't think I have ever seen a little-endian processor numbering bit 0 as the most significant bit. But big-endian processors sometimes names the most significant bit 0, and sometimes the least significant bit.
Hence, even if you do try to use the bit endianness in the discussion, the use of bit0 as least significant can't be used as any proof since it is used by bost little-endian and big-endian processors.
Next thing. If you have a 3-byte instruction, one byte op-code and two byte address, you shouldn't try to merge the opcode with the first byte of the address and imply big or little endian. That is just an ugly extrapolation.