Hello there,
working on a project on motion control with the new LPC1768 in connection with the latest CMSIS I recently noticed the following problem: I wasn't able to get the PWM1 module working with the so called "PWM mode", that is using the shadow register functionality. When trying to write to the LER register of the PWM block there was no change of the value visible within the Keil peripherals monitor.
This got me suspicous, so I looked deeper into the LPC17xx.h of the CMSIS and found the problem. Consider the declaration of the PWM block below. From the LPC17xx user manual one can find the addresses of the registers CR3 (0x40018038) and MR4 (0x40018040). The difference of the addresses yields a gap of 4 bytes in between these two registers, but this is not reflected in the typedef of the PWM block as you can see.
typedef struct { __IO uint32_t IR; __IO uint32_t TCR; __IO uint32_t TC; __IO uint32_t PR; __IO uint32_t PC; __IO uint32_t MCR; __IO uint32_t MR0; __IO uint32_t MR1; __IO uint32_t MR2; __IO uint32_t MR3; __IO uint32_t CCR; __I uint32_t CR0; __I uint32_t CR1; __I uint32_t CR2; __I uint32_t CR3; // Address: 0x40018038 // <- 4 byte dummy var missing here __IO uint32_t MR4; // Address: 0x40018040 __IO uint32_t MR5; __IO uint32_t MR6; __IO uint32_t PCR; __IO uint32_t LER; uint32_t RESERVED0[7]; __IO uint32_t CTCR; } PWM_TypeDef;
So naturally, writing to all registers below CR3 creates errornous behaviour. A workaround is either to modify the header (meh) or simply #def'ing the register addresses manually.
Hope this will be fixed in a next version of the header.
Best regards, Christoph
If you haven't done so already, I would suggest that you inform Keil support of this.
They're normally pretty quick at including simple errors like this at the next release.
It seems that you are using an older header file.
LPC17xx.h header provided in MDK-ARM 4.11 already contains correct PWM_TypeDef.
typedef struct { __IO uint32_t IR; __IO uint32_t TCR; __IO uint32_t TC; __IO uint32_t PR; __IO uint32_t PC; __IO uint32_t MCR; __IO uint32_t MR0; __IO uint32_t MR1; __IO uint32_t MR2; __IO uint32_t MR3; __IO uint32_t CCR; __I uint32_t CR0; __I uint32_t CR1; __I uint32_t CR2; __I uint32_t CR3; uint32_t RESERVED0; __IO uint32_t MR4; __IO uint32_t MR5; __IO uint32_t MR6; __IO uint32_t PCR; __IO uint32_t LER; uint32_t RESERVED1[7]; __IO uint32_t CTCR; } LPC_PWM_TypeDef;