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apb design issue

kevin007 kevin007
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Note: This was originally posted on 13th June 2009 at http://forums.arm.com

Hi,
I have an APB master interface to the configuration registers. The register module is a APB slave which has a differnet clock.

The problem I am facing is, if the APB clock is faster than the register module clock, then how to achieve synchronization between the two clock doamins.

If I use synchronization on the slave clock side, there will be too many signals to be synchronzied. Hence I want to use synchronization on APB side, which will have fewer signals. But, APB has no signal to hold the bus in the case where the data from a write cycle to the slow clock domain has not yet been registered by the slow clock.

Please let me know any suggestions how to achieve the synchronization.
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    Note: This was originally posted on 17th June 2009 at http://forums.arm.com

    Thank you for the reply. But I have to use only APB2.0. So, how the synchronization can be achieved?
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    Note: This was originally posted on 15th June 2009 at http://forums.arm.com

    You could just use the latest AMBA 3 APB spec which has a PREADY signal to support wait states required by your synchronisation logic (it also has a PSLVERR signal to support error indications).

    This newer APB spec is available from ARM's website.

    JD
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    Note: This was originally posted on 18th June 2009 at http://forums.arm.com

    Sorry, simple answer, you can't in the AMBA 2 APB domain.

    For write accesses you could just buffer the write data in the slave and then write it to the destination device at the slave frequency, but read accesses would need synchronisation, which would require a wait signal, which you don't have.

    So unless this is a write only interface, you will need to do any synchronisation before reaching the APB master driving your slave.

    Or that's my thoughts anyway...

    JD