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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Answered

    AXI 4 burst boundary +1

    16293 views
    3 replies
    Latest over 8 years ago
    by Duke Thrust
  • Answered

    Disabling L2 cache for CPU1 (Zynq-7000) +1

    • Cortex-A9
    • Cache
    • L2
    18383 views
    5 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Answered

    Help with programming STM32F103RCT6 board. +1

    • Cortex-M3
    • Cortex-M
    • STM32F
    5533 views
    1 reply
    Latest over 8 years ago
    by MrHarmonSr
  • Answered

    ARMv8 backwards compatibility with ARMv7 0

    • Armv7
    • Armv8-A
    • AArch32
    • Linux
    20510 views
    2 replies
    Latest over 8 years ago
    by arunsvasan
  • Not Answered

    [Cortex-M33 FVP]:SecureFault with SAU disable 0

    • ANSI
    • RTX
    • ACE
    • CHI
    • Security
    • Cortex-M3
    • Keil
    • Cortex-M
    • TrustZone
    • Cortex-M33
    • Armv8-M
    • Memory
    17988 views
    6 replies
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    Virtual IRQ/FIQ exceptions with ARMv8 and no GIC 0

    5772 views
    4 replies
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Suggested Answer

    How NS bit is set in case of DMA transfer ? 0

    • AXI
    • TrustZone
    • Armv8-M
    10149 views
    2 replies
    Latest over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Suggested Answer

    Is there any ARMv8-M platform that support TrustZone? 0

    • TrustZone
    • Armv8-M
    10276 views
    3 replies
    Latest over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Answered

    Non-Secure Software installing SG instructions into Secure Memory 0

    • TrustZone Controllers
    • Controllers
    • TrustZone
    • System Design
    • Armv8-M
    • Block
    • Secure Transactions
    • Memory
    15248 views
    5 replies
    Latest over 8 years ago
    by Gabriel Wang Arm Employee Badge
  • Answered

    How memory type is decided when MMU is disabled ? +1

    7584 views
    1 reply
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Replacing branch-instruction with address assignment to PC 0

    • Cortex-M
    • Arm Assembly Language (ASM)
    • Cortex-M4
    6310 views
    4 replies
    Latest over 8 years ago
    by Raad
  • Suggested Answer

    Control access to L2 cache 0

    5868 views
    5 replies
    Latest over 8 years ago
    by christoph8446
  • Answered

    ARM assembly +2

    • Arm Assembly Language (ASM)
    5993 views
    5 replies
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Can we use same peripheral in secure and non secure world simultaneoulsy ? 0

    • ACE
    • CHI
    • TrustZone
    • Armv8-M
    25361 views
    7 replies
    Latest over 8 years ago
    by Diya Soubra Arm Employee Badge
  • Not Answered

    AHB transfer on Cortex-M3 0

    3572 views
    2 replies
    Latest over 8 years ago
    by mpattaje
  • Suggested Answer

    Setting up an ISR for a PIT timer (homework help) +1

    • Microcontroller (MCU)
    • Cortex-M
    6189 views
    1 reply
    Latest over 8 years ago
    by karthik dharma
  • Suggested Answer

    What is meaning of Logical MMU ? 0

    • TrustZone
    4885 views
    2 replies
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Suggested Answer

    CMSIS DSP - Realtime FIR Filter, Sample by Sample Issue +1

    • Cortex-M
    • CMSIS
    10120 views
    2 replies
    Latest over 8 years ago
    by Duke Thrust
  • Answered

    Which component set the NS bit in SCR ? 0

    • Architecture
    • CHI
    • TrustZone
    • Armv8-M
    11337 views
    2 replies
    Latest over 8 years ago
    by Sahil
  • Answered

    PWM code not running on LPC2129 board but working on logic analyzer . +1

    • Arm7TDMI-S
    5761 views
    1 reply
    Latest over 8 years ago
    by karthik dharma
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Topics being discussed in this forum
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  • AMBA
  • Arm Assembly Language (ASM)
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  • Cache
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