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Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?

AJ

As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode.

I'm curious about the handling of Interrupt Service Routine during the lock-step mode.

When these two cores share same interrupt input, how can they execute same interrupt service routine without occuring lock-step fault?

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  • +1 in reply to AJ

    It is not a few cycles, only a half cycle. It is like a black box. There is one(!) interrupt line, which enters the box. The two cores (actually no master/no checker) get this input and work with it. The delay is needed to find transient issues, so in the end I think it is no difference if half cycle or multiple.
    Important is, that both cores have the very same input.

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  • +1 in reply to AJ

    It is not a few cycles, only a half cycle. It is like a black box. There is one(!) interrupt line, which enters the box. The two cores (actually no master/no checker) get this input and work with it. The delay is needed to find transient issues, so in the end I think it is no difference if half cycle or multiple.
    Important is, that both cores have the very same input.

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