Barriers in in-order cores like cortex-A53, A7

Two different orderings.

When it refers to in order for pipelines, it's talking about the order instructions are fetched, decoded and issued.  That is, these processors will issue the instructions in the order they appear in memory.

Memory ordering is about the order that memory accesses occur in.

Might be easier to understand with an example:

ADD x0, x0, #1
LDR x1, [x2]
LDR x3, [x4]
SUB x5, x5, #1

If we have an in-order pipeline, these instructions will be issued in order.  In other words, the LDRs won't be issued before the ADD.  The SUB won't be issued before the LDRs.  etc...  (If we have a multi-issue pipeline, some instructions might get issued at the same time as each other.  But it won't be "before" the previous instruction)

The memory ordering is different.  Let's assume that the address regions pointed at by x2 and x4 are both marked as Normal, and that the addresses do not overlap.  The architecture does not guarantee that accesses to Normal memory will occur in order.  So even though the LDR instructions were issued in order, the memory accesses that result are still permitted to be out of order.

There are many reasons why a processor might re-order memory accesses.  Such as a result of merging multiple accesses, performing accesses speculatively ahead of time, or want to generate more efficient bus traffic.

Two different orderings.

When it refers to in order for pipelines, it's talking about the order instructions are fetched, decoded and issued.  That is, these processors will issue the instructions in the order they appear in memory.

Memory ordering is about the order that memory accesses occur in.

Might be easier to understand with an example:

ADD x0, x0, #1
LDR x1, [x2]
LDR x3, [x4]
SUB x5, x5, #1

If we have an in-order pipeline, these instructions will be issued in order.  In other words, the LDRs won't be issued before the ADD.  The SUB won't be issued before the LDRs.  etc...  (If we have a multi-issue pipeline, some instructions might get issued at the same time as each other.  But it won't be "before" the previous instruction)

The memory ordering is different.  Let's assume that the address regions pointed at by x2 and x4 are both marked as Normal, and that the addresses do not overlap.  The architecture does not guarantee that accesses to Normal memory will occur in order.  So even though the LDR instructions were issued in order, the memory accesses that result are still permitted to be out of order.

There are many reasons why a processor might re-order memory accesses.  Such as a result of merging multiple accesses, performing accesses speculatively ahead of time, or want to generate more efficient bus traffic.