We are trying test TCM ECC Error ISR, on Cortex R5. But we are failing to get ISR for this fault.
So, can you please clarify on this, whether we have any known issue with this ?? or any fix we have to get this ISR reported.
We are using this below sequence
void corrupt_a_tcm() { //; Setup - these addresses MUST be doubleword aligned asm("LDR r10,=0x0000F100"); //; Address of victim TCM location to insert error asm("LDR r6,=0x0000F108"); //; Address of scratch memory location (r6, NOT r11/fp - see above) asm("LDR r0,=0xDEAFBEEF"); asm("LDR r1,=0xCAFEBABE"); asm("STR r0,[r10]"); asm("STR r1,[r10,#0x4]"); //; Disable ECC - ATCM asm("MRC p15,0,r0,c1,c0,1"); //; Read aux ctl asm("BIC r0,r0,#0x02000000"); asm("MCR p15,0,r0,c1,c0,1"); //; Memory barrier to ensure SQ is empty - otherwise data may come from other ; sources and not get corrupted in the way we want asm("DMB"); //; Read data and introduce ECC error asm("LDRD r0,[r10]"); //; Read data to corrupt asm("STRD r0,[r6]"); //; Store data to corrupt in scratch location asm("LSR r2, r0, #16"); //; Only interested in 3rd byte asm("EOR r2, #0x2"); //; Toggle one bit asm("STRB r2,[r6,#2]"); //; Store byte to corrupt data and ECC asm("LDRD r0,[r6]"); //; Load corrupted data back to set up internal registers asm("BFI r0, r1, #0, #8"); //; Merge byte 0 from upper word into lower word asm("ROR r0, r0, #24"); //; Shift byte 3 into byte 0 position, byte 0 into byte 1 position. asm("STRH r0, [r10,#3]"); //; Store byte - data unchanged, but ECC changed //; Enable ECC asm("MRC p15,0,r0,c1,c0,1"); //; Read aux ctl asm("ORR r0,r0,#0x02000000"); asm("MCR p15,0,r0,c1,c0,1"); //; Read data - should get corrected from 0xDEAFBEEF to 0xDEADBEEF asm("LDRD r0,[r10]");}