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order problem

Tom T 6 months ago

Hi All, I have two questions related to axi. In system, I have one master ,one interconnect and one slave.
Q1: If master send write transaction to slave -> DMB-> send read transcation to slave, the order seem by slave should be same as older seem by master?
Q2:How about If master don't use DMB, just wait bresp and then send read transcation. the order seem by slave is same as master? will it happen reorder case?
Thanks a lot!

Top replies

Martin Weidmann 6 months ago +1 suggested

I think you're mixing up two things: How software expresses what it wants. How the hardware achieves what software asked for. Issuing a barrier is software saying that it wants ordering for these...
Martin Weidmann 6 months ago in reply to Tom T +1 suggested

Tom T said: But If the master write transaction to slave -> wait brsp and then send read transaction to slave. it can not ensure that the slave must receive the write transaction first and then read transaction...
Martin Weidmann 6 months ago in reply to Tom T +1 suggested

Broadly yes - but you should refer to the AMBA AXI specification ( https://developer.arm.com/documentation/ihi0022/latest , A4.3 - Memory types) for the detailed description. For example, there is also...