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I need support to initialize GICv2 on ARM A53 Dual Core processor environment in Non Secure mode.

Edoardo

Hi, I'm trying to initialize the GICv2 interrupt controller to manage interrupts coming in the systems.

At the moment I'm not able to receive interrupts on the CPU.

It seems to me that these interrupts are pending only in case I have Group0 enabled (GICD_CTRL.bit0) but when I have Group1 enabled (GICD_CTRL.bit1) these are not propagated.

To see interrupt pending I'm looking at register GICD_ISPENDRn.

This is the first time I'm programming GICv2 and I'm using low level code.

Can you support on this?

Do you have a sequence of programming operations to be implemented for the configuration in Non Secure mode?

At the moment I'm considering the GICv2 interrupt controller but probably I need to enable the interrupts on the A53 (Core0).

Thanks a lot for your support.

Best regards Edo.