What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?
In ARM's white paper(about the cortex-A7 and cortex-A15) says as follow:
I want ask the in-order and out-of-order mean what?
If you Google 'Out of order execution' you should get lots of hits that go into it in some detail. I'll just give a very hand wavey explanation in terms of building a house.
An engineer might produce a list of things to be done to complete a house and send them off to be agreed with some auditor. Actually they don't do that but we'll just say that for this explanation. The actual construction will not be done in the exact order given by the list of things to do. Instead bits will be done when all the prerequisites are satisfied and there's available people to do them. For instance the electrics might go in at the same time as plumbing. To make it closer to what happens with computers though suppose the auditor expects that the stages will be completed in order or will say it isn't being built to the agreed standard. In that case whenever the auditor comes along any work before a certain stage will need to be completed and any work after it destroyed or ripped out.
This is what happens with an out of order processor. The instruction stream is predicted and read in advance of the completed instructions. Dependent instructions can be executed after the ones they depend on are completed. For instance an add after a divide might be executed before the divide ends because it does not depend on the result of the divide. If there is an interrupt a consistent state has to be ensured and that is accomplished by throwing away any results after a gap of any instructions that haven't been completed. A special problem is that compared to building the house the predictions may not be correct. A branch might be predicted to be true but when the condition is actually evaluated it turns out it is false so any work done using that prediction has to be thrown away. It is like the builder going and building gable windows before the engineer has actually decided what type windows are required. If the builder is correct the building is completed sooner - that sort of thing is rare in building but is done all the time in out of order processors.
Thanks very much for your answer!
But I also want to ask the cortex-A7's in-order mean that the instruction send to the five entries one by one? But ARM says that cortex-A7 is dual issue, so I think this understand is not right. What's the correct understand?
Hello,
the word "order" of "in-order" or "out-of-order" means the order of the instructions of the program.
Each instruction is decoded in-order and stores into the decoded instruction buffer (aka the central window) in-order.
However, the extraction (i.e. issuing) from the decoded buffer might not be in-order.
For the in-order pipeline, the issuing should be in order.
The "dual issue" means at maximum sequential two instructions can be issued.
For the out-of-order pipeline, the issuing might not be in order.
The "triple issue" means at maximum three instructions can be issued ignoring the program order.
However the out-of-order issuing is so designed that there will not happen inconsistency from the program order view point.
Best regards,
Yasuhiko Koumoto.
Thanks very much!
You give me so much help!