How can I know if an ELF file is for Cortex-A or Cortex-M?

Hello,

I have a question when doing the binary analysis. For a given ELF file (hello.elf) that has already been identified for the ARM architecture, how can I quickly know if this ELF is for Cortex-A or Cortex-M? More specifically, I'm trying to identify the whole bare-metal images (or RTOS images like FreeRTOS) for the Cortex-M.

From the result of "file hello.elf":

% file hello.elf
hello.elf: ELF 32-bit LSB executable, ARM, EABI5 version 1 (SYSV), statically linked, with debug_info, not stripped

We can only see that this ELF is for ARM.

And from the result of "readelf -h ./hello.elf":

% readelf -h ./hello.elf
ELF Header:
  Magic:   7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 
  Class:                             ELF32
  Data:                              2's complement, little endian
  Version:                           1 (current)
  OS/ABI:                            UNIX - System V
  ABI Version:                       0
  Type:                              EXEC (Executable file)
  Machine:                           ARM
  Version:                           0x1
  Entry point address:               0xcb5
  Start of program headers:          52 (bytes into file)
  Start of section headers:          150896 (bytes into file)
  Flags:                             0x5000200, Version5 EABI, soft-float ABI
  Size of this header:               52 (bytes)
  Size of program headers:           32 (bytes)
  Number of program headers:         5
  Size of section headers:           40 (bytes)
  Number of section headers:         19
  Section header string table index: 17

It's also only showing this file is for the ARM architecture.

So are there any other approaches that can quickly identify the target architecture of an ELF file?

Thank you for your time!

Parents
  • Maybe check out the section addresses?  Cortex-M has (flash) code usually in 0-1fffffff, with RAM at 2000000-3fffffff or (external) 60000000-9fffffff, while don't most Cortex-A chips typically have all-ram architectures without the explicit "banks" of memory.  (OTOH, Cortex-A will also have an MMU can I guess they could  put their section starts whereever they want, including at Cortex-M-compatible locations?)

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  • Maybe check out the section addresses?  Cortex-M has (flash) code usually in 0-1fffffff, with RAM at 2000000-3fffffff or (external) 60000000-9fffffff, while don't most Cortex-A chips typically have all-ram architectures without the explicit "banks" of memory.  (OTOH, Cortex-A will also have an MMU can I guess they could  put their section starts whereever they want, including at Cortex-M-compatible locations?)

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