Need a uvm testbench that can handle payload data, valid, and ready signaling. Where to download an example testbench ?

Hi,

I have an RTL design with generic payload data width and it has the "valid" and "ready" handshake signals.

so this is a basic AXI type of interface.

Does anyone know of a simple systemverilog or uvm testbench that can exercise and validate the functionality of the design ?

Thanks,

David