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Now i am focusing on the apb 2.0 specification.
How to perform a continuous transfer in apb 2.0 . I read some forum , But i did't get a idea.
If anyone know the continuous transfer in apb 2.0 ,Please share the waveform . It;s easily understand for me.
For my understanding :
First clock i am setting setup phase (paddr,pwrite,pwdata,psel) , then the second clock cycle setting the access phase(penable).
Third clock cycle disable the penable, psel . This is for normal write operation.
In continuous transfer third clock cycle stable the psel high and disable the penable for one clock period ?
third clock cycle psel and penable stabel high ?
Which one is the correct.............
Thanks in Advance
Your first description is correct.
For a continuous sequence of APB accesses to the same peripheral, PSEL would remain high and PENABLE would be de-asserted for one cycle at the start of each individual APB access to indicate the "setup phase".
See figure 4-1 in the APB protocol documentation, which shows the APB state diagram. When you are in the "ACCESS" bubble (PSEL=1 and PENABLE=1) and completing an access (PREADY=1), to perform another access immediately you follow the arrow on the right taking you immediately back to the "SETUP" bubble where PSEL=1 and PENABLE=0.