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According to spec IHI0022D_amba_axi_protocol_spec section A2.1 page number: A2-28
"All signals are sampled on the rising edge of the global clock "
Q) Should RESET_N also be sampled on the rising edge only?
Section A3.1.2, says
"The AXI protocol uses a single active LOW reset signal, ARESETn. The reset signal can be asserted asynchronously, but de-assertion must be synchronous with a rising edge of ACLK.
During reset the following interface requirements apply:• a master interface must drive ARVALID, AWVALID, and WVALID LOW
• a slave interface must drive RVALID and BVALID LOW
Q) How a design should implement with respect to reset. ( Should it implement Asynchronous reset)?
When ARESETn is asserted (low) this should immediately reset any registers it is connected to, so the output is immediately cleared. This means that it doesn't require the clock to be running to get any register into a reset state.
When reset is asserted (low) the protocol requires all masters and slaves hold any xVALID outputs low so that no transfers are being signalled.
However ARESETn needs to be de-asserted (high) synchronous to an ACLK rising edge so that all AXI components then have a full ACLK cycle of setup time for their ARESETn input before it is sampled.
So ARESETn can be asserted asynchronously, but the reset controller logic then needs to de-assert ARESETn synchronously.