By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence
This is Part 3 of a 4 part series. Links below
We have seen how a systematic process can be applied to validating SoC performance using UVM testbenches. The results then need to be analyzed ideally using a graphical tool.
The Cadence Interconnect Workbench is a tool built for automating this complex process. It provides a number of automation and analysis features specifically designed to make this complex task relatively straightforward. Figure 7 shows a high-level view of Interconnect Workbench capabilities.
Figure 7: Cadence Interconnect Workbench Flow
Interconnect Workbench offers a number of flows that can be used with either manually created UVM testbenches or automatically created testbenches from the IP-XACT output from Corelink AMBA Designer or from an Excel spreadsheet. It provides traffic generation capabilities on top of the VIP that enable quick and easy modelling of the different traffic classes, and automatically generated test suites for “out-of-the-box” regressions. Interconnect Workbench also provides a comprehensive graphical analysis tool for post-processing the results of performance validation regressions with a huge capacity for handling hundreds of thousands of transactions.
Figure 8 shows the default overview chart generated by the performance analyzer
Figure 8: Performance Analysis Overview
Mobile SoC platforms are complex SoCs with hundreds of IP functions all connected to a common memory system using a large number of complex system IP functions. The architecture and implementation of these types of systems is a tricky balancing act of providing just enough performance for a given silicon and power budget. It is a very challenging task to validate the implemented system against a set of performance requirements. This validation needs to be done at the register transfer level (RTL) to achieve the necessary accuracy. Without automation and analysis tools this task is onerous and as systems continuously increase in complexity the job only gets tougher.
Cadence Interconnect Workbench is a comprehensive package of tools that deliver testbench automation, test automation and performance analysis for substantial performance regressions. Using Interconnect Workbench enables rapid turnaround of RTL feature changes against use cases and thus provides insight and knowledge that otherwise would be extremely difficult to acquire.
William Orme, Strategic Marketing Manager for System IP, Processor Division, Arm is responsible for the CoreLink NIC-400 and the next generation on-chip interconnect. At Arm since 1996, he has lead the introduction of many new products, including the ETM and subsequent CoreSight multi-core debug and trace products. Prior to joining Arm, William spent 12 years designing embedded systems from financial dealing rooms, through industrial automation to smartcard systems. William holds degrees in electronics and computer science as well as an MBA.
Nick Heaton, Distinguished Engineer, Systems and Verification Group, Cadence Design Systems is an ASIC and EDA veteran with more than 25 years of experience in the design and verification of complex SoCs. Nick graduated from Brunel University, London in 1983 with First Class Honors in Engineering and Management Systems, initially working as an ASIC designer for ICL in Bracknell. In 1993, he founded specialist ASIC Design and Verification Company Excel Consultants, servicing customers such as Arm and Altera. In 2002, Nick joined Verisity (now Cadence) as Manager of Northern European Consulting Engineering.
Nick currently works in the Cadence Research & Development organization as a Distinguished Engineer with special responsibility for the Cadence Interconnect WorkBench.
In case you missed them, find previous parts to this blog series below:
How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 1
How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 2
How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 3
Cadence System Design and Verification