Arm and Samsung Foundry Extend Design Partnership on 11LPP FinFET Node

At the Samsung Foundry Forum last year, Arm showcased its collaboration leading up to, and including, its successful 14nm FinFET partnership. Even at that time, the Artisan IP on Samsung Foundry’s 14nm node was in high volume production. Samsung Foundry gave us the opportunity to discuss what we saw in the markets beyond 14nm, including the automotive and Internet of Things (IoT) sectors. In the same event, Samsung Foundry showed a clear path down to smaller nodes using some incredible technology to print incredibly tiny features.

One year later, our collaboration continues with a broader scope and a faster pace than ever. Together, Arm and Samsung Foundry have just announced their plans for Artisan Physical IP at the 11LPP (11nm Low Power Plus) FinFET node. While 11LPP is firmly rooted in 14nm, the Artisan IP offering is broader and targets the more traditional markets for Arm and Samsung Foundry—mobile and high-performance networking—along with an expansion into the automotive and IoT markets.

“Samsung Foundry and Arm have collaborated from the first generation 14nm FinFET process to enable multiple successes across consumer, infrastructure and automotive segments,” said Ryan Lee, vice president of Marketing Team at Samsung Electronics. “Building on this high-volume 14nm node, we have expanded the platform offering to our advanced 11LPP process with the Arm Artisan foundation IP platform. New features including segment-specific standard cells for ultra-high density and highest performance as well as a broad automotive platform and compute solutions will enable our partners to move quickly to market with differentiated products across various applications.”

In the beginning of this year, Samsung Foundry strengthened its foundry customer support with new SAFETM (Samsung Advanced Foundry Ecosystem) program. Arm is one of the strategic members of SAFE, giving the ecosystem and customers access to leading co-optimized physical IP solutions to enhance next-generation SoC designs.

11LPP Features and Benefits

The 11LPP process is a shrink from 14LPP/LPC (Low Power Cost). We expect 11LPP to have a long life, and as such, the 11LPP process targets more market segments. Automotive support and the inclusion of the high-end wearable market significantly widens the target markets for 11LPP.

Customers who want to move forward in process nodes, but don’t want the full costs associated with non-shrink nodes will find 11LPP to be a wise step after 14nm. This move will enhance their power, performance and area for less cost than advancing to the next full node. Or, partners ready for automotive designs in a FinFET process (which is perfect for automotive–dense designs, high performance, and the ability to limit power by running at low voltages with minimal performance impact) can move to 11LPP, which provides Automotive Grade 1 add-on and ASIL-B support.

Physical IP Platform Overview for Samsung 11LPP

The Artisan foundation IP is foundry-sponsored for 11LPP and is significantly expanded when compared to 14LPP.

Logic libraries include an entirely new standard cell architecture for ultra-high-density (UHD) architecture, which also supports multi-height designs. This is ideal for power-sensitive and/or cost-sensitive designs. Cell sets across architectures have expanded to meet the needs of designs across market segments and include cells with optimizations for area, extreme low power, and high performance.

Memory compilers have a wide-range of optimization points, echoing the logic libraries for the best overall physical IP solution. The compilers output instances that can solve power issues with multiple Vt periphery options, giving users compile-time control over the performance-power targets of a given size; progressive power gating modes and read/write assist schemes to support low voltages and improve DVFS capabilities. Supporting a wide range of applications from networking to mobile to IoT, the Artisan memory compilers simplify SoC design with a large selection of standard, low power and yield optimization features.

Completing the platform, the 11LPP GPIO library is fully programmable, designed for 1.8V and supporting operation down to 1.2V. Its flexible configuration supports dual-row in-line or dual-row staggered, all using the same physicals.

All of the aforementioned products have add-ons that support Automotive AECQ100 Grade 1 design requirements. In addition, the platform comes with ASIL-B support, and a complete Automotive Safety Package.

To assist in optimum core implementation, the platform includes Arm POP IP. POP IP enables fastest time to market of advanced Arm Cortex-A series cores, using Artisan logic libraries, fast cache memory instances, and implementation utilities to further optimize the CPU and speed-up time to market. POP IP will be available for Cortex-A75 and Cortex-A55 based computing systems, including Arm DynamIQ.

Arm Artisan IP Availability

Arm physical IP platform for 11LPP is available for access now for lead customers.

For more information, please contact Arm Physical Design Group or visit the Arm Physical IP webpage.

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