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In armv8 specification, I have found two types of exclusive access instructions: LDAXR/STLXR and LDREX/STREX. I have some questions about these instructions:
(1) What's the difference between these exclusive access instructions?
(2) Is LDREX/STREX only for non-cacheable memory?
(3) Is LDAXR/STLXR only for cacheable memory?
I have tried LDAXR/STLXR, When I perform a exclusive read to a shared cacheable memory location and then perform a exclusive write to this address, It seems fine and STLXR return status (w2) is 0, as expected. the part of code is below:
MOV x0, #0xd1000000 // this is a shareable cacheable address
LDAXR x1, [x0] // exclusive read
LDR w1, =0xabcd1234
STRXR w2, w1, [x0] // exclusive write
But When I perform a exclusive read to a shared non-cacheable address location i.e. DDR, this will response EXOAKY, and the perform a exclusive write to this address, it didn't response EXOKAY but OKAY ( w2 is 1), thus the exclusive write is failed. I don't know why.
MOV x0, #0x40000000 // this is a shareable non-cacheable address (DDR)
check out the ARMv8-A progrmmers guide. It contains a good explanation.
Thank you for reply!
I have read the ARMv8-A programmer's guide, and I found more explain about LDAXR/STLXR, it seems that this instruction is only for shareable cacheable memory, am I right?
But I find nothing about LDREX/STREX, so what's the difference?
While LDAXR has an implicit synchronization, LDREX/STREX is just an exclusive access to an address. You will need a data barrier such as DMB to make sure all CPUs see the same value.