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I'm using DMA transfering data through ACP on A53.
According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?
Then software must re-configure DMA then re-start the transmission for next 64B data?
Or DMA connects to ACP should do some special design to automatically divide DMA transfer size into multiple ACP bust size then finish the multiple ACP transaction without software involved?
thanks in advance.
Of course, you do not have to program the DMA in chunks of 64bytes. Maybe speed can be improved if you align source/destination but this is a different story.
I was told by our hardware engineer about that information. I also doubt the behavior. So a regular DMA through ACP port should have transfer size larger than ACP burst size, right?
As I understand it from the UltraScale+ TRM, the ACP must be served in multiples of 64 or 16 bytes. So you cannot send 120 bytes via DMA via ACP, but 128. Anyway I'd recommend to ask the FAE of the SoC you want to use.
I have same understand with you, form A53 TRM and some search on internet. But on our DMA design, it is fixed to 64bytes, multples 64 doesn't work. So I come here trying to get confirmed information. I don't use a SOC, we have A53 core only.
Out of curiosity: If you do your own design with a A53, shouldn't you get those questions answered directly from ARM?
Hardware team provide such DMA design to me to write firmware with. But I don't know why DMA can't increase src/dst address by itself, instead it requires firmware to do such a process. That makes no sense for a DMA.
I agree. If you have to do so every 64bytes, you can likely do faster using NEON vector load/store (16bytes a time).
I saw you mentioned UltraScale+, have you tried DMA+ACP on that platform? Can DMA transfer larger size than 64Bytes in one chunk?
Sorry, I did not work with DMA on the US+ yet.