shareability attribute for armv8 cortex a-53


I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

My question is how should I interpret the shareability domain: inner, outer controlled through TCR register and the page descriptor. Would be that inner shareable is within the Cluster and only within it the Coherency is maintained for the Memory region marked Cacheable WB-WA for Innter and Outer?

Or is my understanding wrong in the context of "Snoop and Maintenance Requests" chapter of  "ARM Cortex-A53 MPCore Processor TRM". It says there that broadcastinner asserted enforces broadcastouter asserted so that would suggest that setting the inner shareability makes snoop and maintenance requests boradcast to the Observers in both Inner and Outer Domains. 

Please help!