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I have some questions about DMB and DSB in armv8.
In armv8 Reference Manual doc, it says "The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order".
But in ARM Cortex-A Series Programmer’s Guide for ARMv8-A doc, it explains some dmb/dsb parameters.for example :
<option> | Ordered Accesses (before – after) | Shareability Domain LD | Load –Load, Load – Store | Full system
Load - Load/Store:This means that the barrier requires all loads to complete before the barrier butdoes not require stores to complete. Both loads and stores that appear after thebarrier in program order must wait for the barrier to complete.
Since Load - Load/Store means the barrier requires all loads to complete before the barrier, I think it has ensured the completion of memory access, so I am confused.
In ARM Cortex-A Series Programmer’s Guide for ARMv8-A doc, it also says DSB "enforces the same ordering as the Data Memory Barrier, but has the additional effect of blocking execution of any further instructions, not just loads or stores, or both, until synchronization is complete".
Since DSB can block any instructions, what's "ST" in "DSB ST" for?
I have already knew that DSB can replace DMB safely, but in what situation should we only use "DSB", not "DMB"? what's the difference between DSB and DMB? An example should be great.
(1) Completion != order. For example, if you write to register A then B then C. This order can be changed by the memory system for many reasons (cache, bus etc.). If you place a DMB after each store, you can be sure, that C will not be written before B and A. But you cannot be sure about the "when".
(2)/(3) If the code after the store depends on the effect of the store, you need DSB. For example if you write to some peripheral and want to be sure it will not generate interrupts before enabling them in the interrupt controller.
Hi 42Bastian Schick :
Very thanks for the examples!
There are other questions that confusing me.
(1) According to ARMV8 reference Manual, DMB seems to ensure that all affected memory accesses are Observed-by each PE.
but I don't understand the difference between visibility and completion. Can you give me an extra example to explain in which situation memory access is visible but hasn't been completed?
(2) In "DSB ST", does that mean the DSB instruction only block loads and stores? Not all instructions?
Regarding "ST", the architecture document listed the following options (This is from Armv7 version of Arm ARM, not v8, I don't have that document with me right now),
Regarding DSB vs DMB, since DMB only ensure the ordering between memory accesses, if the 2nd instruction is not a memory access instruction but you need to ensure the ordering, you need to use DSB rather than DMB. For example, after you write to a peripheral register and then enter sleep mode (WFI/WFE), adding a DSB between them make sure the write come out of the processor's write buffer before entering sleep.
Thank your for the reply.
I am still trying to understand the difference between observation and completion of memory access, but have not got the point. It seems difficult for me to understand. Can you give me a hand?
One more additional aspect about completion is that for transfers that are not cached not buffered (e.g. reading a peripheral register), the completion happens when the processor received the response of the transaction (e.g. OKAY/ERROR). Depends on the bus system design, the response received from the transfer could be different from the order of the data reaching the memory system.
Thank you very much!
It helps me a lot.