Cortex A9 SCU Control Register Enable bit 0 or 1 for enable changed in Manual from g to h?

The Cortex-A9 MPCore Technical Reference Manual Revision: r4p1

describes the Bit 0 of scu-control-register  as   0 SCU enable 1 SCU disable. (this is Version i of the manual)

In Version g of the manual ist the other way round (1 SCU enable 0 SCU disable).

https://developer.arm.com/docs/ddi0407/i/snoop-control-unit/scu-registers/scu-control-register

is the new or the old version correct?

There is no mention of this change in the Revision History of the manual.