Barrier after access to memory mapped register?

Hi,

Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from the interrupt status register of the peripheral when processing the interrupt. I understand the use of the barrier when accessing main RAM, but does it make sense for registers?

CPU: A53 aarch64

Thanks

Parents Reply Children
No Data