CM3 DesignStart Build warning messages with Quartus Prime 17.0.2

Hi,

I am using Quartus Prime Lite 17.0.2 for building Cortex-M3 DesignStart RTL.

I can successfully build the RTL, but I got some critical warnings as follows. Can I ignore these warnings? Is there any effects on the design by these warnings?

Critical Warning (308042): (High) Rule C105: Clock signal should be a global signal. (Reporting threshold:25). Found 2 node(s) related to this rule.

Critical Warning (308024): (High) Rule R101: Combinational logic used as a reset signal should be synchronized. Found 2 node(s) related to this rule.

Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 1134 asynchronous clock domain interface structure(s) related to this rule.

Critical Warning (308067): (High) Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 212 asynchronous clock domain interface structure(s) related to this rule.