Cortex-M0 DesignStart R2

For the last weeks, I have been trying to get this new version to work. I did the same as with the previous version and now it is running on the Xilinx Nexys4. However, honestly I do not have any idea how to get the debugging to work. I defined the pins for SWD and connected to an Segger J-Link, but no connection was possible. There is the configuration option ‘define ARM_CMSDK_INCLUDE_JTAG. In removed this, no success. I changed to ‘define ARM_CMSDK_INCLUDE_SWD, no success. I am running out of ideas.

It seems I am missing something important.

Kind Regards

Eberhard Binder

Parents
No Data
Reply
  • Hi, everybody

    I can't help to share my experience here

    I worked out M3 eval with JLINK SWD on zynq7020 board, by following steps in this discussion

    so, I make some comments of issue I came across

    1,check if the tck is drived properly, if you update pinloc or top inout

    2,do not modify the simple flash first, if come across resources issue in fpga, just downsize is OK

    3,the reset is already connected properly in designstart eval, so do not modify it first

    4,run a cxdt pattern first, it's helpful, helping you check your connection

    5,configure MDK as posted in this discussion,and the link community.arm.com/.../swd-issue-in-cortex-m0, don't select erase or program or device

    6,once you see ID in swd, you almost done it!

    thanks for ,Eberhard Binder, 's help

     

Children
No Data