CMSDK - design multi-master bus

 asked: "with the M3 designstart CMSDK, is it possible to design multi-master bus? In the IoT Cortex-M TRM, only an ahb-lite structure is illustrated. That document does mention AHB and APB expansion through INTEXP[1:0] but what if there are more than two masters I need to support?"

  • Hi Wenkwei,

    The SSE-050 subsystem in the Cortex-M3 DesignStart example uses a multi-layer AHB-Lite interconnect. As you observe it has 2 expansion ports available (one is needed for the FPGA infrastructure if you need to keep the option of prototyping).

    When you need to connect several additional AHB masters to your system, there are two ways you could do this - the best choice depends on how your system needs to perform and the level of activity performed by the masters:

    • If you really need to, it is possible to replace the interconnect and make your own version of the subsystem. This is a complicated task, but would allow you to support simultaneous transactions between your additional masters (and the processor) with minimal delays caused by contention of the interconnect. You will still be restricted to only one master being able to access any slave port at a time.
    • If your additional masters can reasonably contend for access amongst themselves, you can use CMSDK to generate an interconnect with several slave ports, one master port and connect this to INITEXP0 or INITEXP1.

    There are other ways that you can enable messages to be passed between different parts of the system, by designing slave components which interface to more than one master - you have a lot of flexibility to optimise your design to the specific solution which you're developing. It's important to check that the latency and throughput of the final choice work in your product and give a good power and area performance at the same time.

    Sean